def _declr(self): assert self.HAS_R or self.HAS_W, "has to have at least read or write part" self.addr = VectSignal(self.ADDR_WIDTH) DATA_WIDTH = self.DATA_WIDTH if self.HAS_W: self.din = VectSignal(DATA_WIDTH) if self.HAS_R: self.dout = VectSignal(DATA_WIDTH, masterDir=DIRECTION.IN) self.en = HandshakeSync() if (self.HAS_R and self.HAS_W) or (self.HAS_W and self.HAS_BE): # in write only mode we do not need this as well as we can use "en" if self.HAS_BE: assert DATA_WIDTH % 8 == 0, DATA_WIDTH self.we = VectSignal(DATA_WIDTH // 8) else: self.we = Signal() if self.HAS_W and self.HAS_BE: self.do_accumulate = Signal() self.do_overwrite = Signal() if self.HAS_R and self.HAS_BE: assert self.DATA_WIDTH % 8 == 0 self.dout_mask = VectSignal(self.DATA_WIDTH // 8, masterDir=DIRECTION.IN)
def _declr(self): super(AddrDataHs, self)._declr() self.addr = VectSignal(self.ADDR_WIDTH) self.data = VectSignal(self.DATA_WIDTH) if self.HAS_MASK: assert self.DATA_WIDTH % 8 == 0, self.DATA_WIDTH self.mask = VectSignal(self.DATA_WIDTH // 8)
def _declr(self): addClkRstn(self) self.a = VectSignal(8) self.b = VectSignal(8)._m() self.c = VectSignal(8) self.d = VectSignal(8)._m()
class ConstCondition(Unit): def _declr(self): self.clk = Clk() self.a = VectSignal(2) self.b = VectSignal(2) self.c = Signal()._m() def _impl(self): one = self._sig('one', Bits(1)) intermed = self._reg('intermed', Bits(1)) one(1) self.c(intermed) If( one._eq(1), If( self.a._eq(1), intermed(1), ), If( self.b._eq(1), intermed(0), ), If( self.b._eq(2), intermed(1), ), )
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.read = Signal() self.write = Signal() self.be = VectSignal(self.DATA_WIDTH // 8) self.dwr = VectSignal(self.DATA_WIDTH) super(Mi32AddrHs, self)._declr()
def _declr(self): self.data = VectSignal(self.DATA_WIDTH) self.keep = VectSignal(self.DATA_WIDTH // 8) if self.USE_STRB: self.strb = VectSignal(self.DATA_WIDTH // 8) self.relict = Signal() self.last = Signal()
def _declr(self): addClkRstn(self) self.input = VectSignal(self.DATAIN_WIDTH, signed=True) self.output = VectSignal(self.DATAIN_WIDTH, signed=True)._m() self.target = VectSignal(self.DATAIN_WIDTH, signed=True) self.coefs = HObjList( VectSignal(self.COEF_WIDTH, signed=True) for _ in range(4))
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.append = Signal() self.data = VectSignal(self.DATA_WIDTH) # an address where the item was stored self.addr_ret = VectSignal(self.ADDR_WIDTH, masterDir=DIRECTION.IN) HandshakeSync._declr(self)
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) self.data = VectSignal(self.DATA_WIDTH) Axi_strb._declr(self) self.last = Signal() Axi_hs._declr(self)
def _declr(self): self.clk = Signal() self.rst = Signal() self.en_mult = Signal() self.en_sum = Signal() self.input = VectSignal(self.width * self.size) self.output = VectSignal(self.width, signed=True)._m() for i in range(self.size): setattr(self, f"kernel_{i}", VectSignal(self.width)) self.multiplier = HObjList( FixedPointMultiplier( width=self.width, layer_id=self.layer_id, unit_id=self.unit_id, channel_id=self.channel_id, process_id=self.process_id, pixel_id=i, log_level=self.log_level + 1, ) for i in range(self.size)) name = f"ConvUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): assert isPow2(self.DEPTH - 1), ( "DEPTH has to be 2**n + 1" " because fifo has have DEPTH 2**n" " and 1 item is stored on output reg", self.DEPTH) self.dataIn_clk = Clk() self.dataOut_clk = Clk() with self._paramsShared(): with self._associated(clk=self.dataIn_clk): self.dataIn_rst_n = Rst_n() with self._associated(rst=self.dataIn_rst_n): self.dataIn = self.intfCls() with self._associated(clk=self.dataOut_clk): self.dataOut_rst_n = Rst_n() with self._associated(rst=self.dataOut_rst_n): self.dataOut = self.intfCls()._m() f = self.fifo = FifoAsync() f.IN_FREQ = self.IN_FREQ f.OUT_FREQ = self.OUT_FREQ DW = self.dataIn._bit_length() - 2 # 2 for control (valid, ready) f.DATA_WIDTH = DW # because the output register is used as another item storage f.DEPTH = self.DEPTH - 1 f.EXPORT_SIZE = self.EXPORT_SIZE f.EXPORT_SPACE = self.EXPORT_SPACE SIZE_W = log2ceil(self.DEPTH + 1 + 1) if self.EXPORT_SIZE: self.size = VectSignal(SIZE_W, signed=False) if self.EXPORT_SPACE: self.space = VectSignal(SIZE_W, signed=False)
def _declr(self): self.din0 = VectSignal(self.WIDTH) self.dout0 = VectSignal(self.WIDTH)._m() if self.WIDTH >= 3: self.din1 = VectSignal(self.WIDTH) self.dout1 = VectSignal(self.WIDTH)._m()
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) self.index = VectSignal(self.INDEX_WIDTH) if self.WAY_CNT > 1: self.way = VectSignal(log2ceil(self.WAY_CNT - 1)) HandshakeSync._declr(self)
def _declr(self): w = self.DATA_WIDTH sig = bool(self.SIGNED) self.inputs = HObjList( VectSignal(w, sig) for _ in range(int(self.ITEMS))) self.outputs = HObjList( VectSignal(w, sig)._m() for _ in range(int(self.ITEMS)))
def _declr(self): super(InsertIntf, self)._declr() self.hash = VectSignal(self.HASH_WIDTH) self.key = VectSignal(self.KEY_WIDTH) if self.DATA_WIDTH: self.data = VectSignal(self.DATA_WIDTH) self.vldFlag = Signal()
def _declr(self): self.ci = Signal() # [possible improvement] you can use io = lambda : VectSignal(self.p_wordlength) as macro # so you do not have to repeat same code self.a = VectSignal(self.p_wordlength) self.b = VectSignal(self.p_wordlength) self.s = VectSignal(self.p_wordlength)._m() self.co = Signal()._m()
def _declr(self): self.ci = Signal() self.a = VectSignal(self.p_wordlength) self.b = VectSignal(self.p_wordlength) self.s = VectSignal(self.p_wordlength)._m() self.co = Signal()._m() self.fa = HObjList([FullAdder() for _ in range(self.p_wordlength)])
def _declr(self): self.param_a = VectSignal(15) self.param_b = VectSignal(15) self.output = VectSignal(self.width * 2 - 1)._m() name = f"ConcatValuesL{self.layer_id}I{self.index}" self._name = name self._hdl_module_name = name
def _declr(self): # fundamentals self.channel = VectSignal(self.CHANNEL_WIDTH) self.error = VectSignal(self.ERROR_WIDTH) Handshaked._declr(self) # packet transfer signals self.endOfPacket = Signal() self.startOfPacket = Signal()
def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.rd = Signal() self.wr = Signal() self.ardy = Signal(masterDir=DIRECTION.IN) self.be = VectSignal(self.DATA_WIDTH // 8) self.dwr = VectSignal(self.DATA_WIDTH) self.drd = VectSignal(self.DATA_WIDTH, masterDir=DIRECTION.IN) self.drdy = Signal(masterDir=DIRECTION.IN)
def _declr(self): self.data = VectSignal(self.DATA_WIDTH) self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) self.src_rdy_n = s() self.dst_rdy_n = s(masterDir=DIRECTION.IN) self.sof_n = s() self.eof_n = s() self.eop_n = s() self.sop_n = s()
def _declr(self): self.clk = Signal() self.rst = Signal() self.en_mult = Signal() self.en_sum = Signal() self.en_channel = Signal() self.en_batch = Signal() self.en_act = Signal() self.input = VectSignal(self.input_width) self.output = VectSignal(self.output_width)._m()
def _declr(self): self.clk = Signal() self.rst = Signal() self.en_pool = Signal() self.input = VectSignal(self.width * 4) self.output = VectSignal(self.width)._m() name = f"MaxPoolUnitL{self.layer_id}" self._name = name self._hdl_module_name = name
def _declr(self): self.id = VectSignal(self.ID_WIDTH) self.addr = VectSignal(self.ADDR_WIDTH) # len is number of words -1 self.len = VectSignal(log2ceil(self.MAX_LEN)) # rem is number of bits in last word which is valid - 1 self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) HandshakeSync._declr(self)
def _declr(self): # DDR data to write self.data = VectSignal(self.DATA_WIDTH) # DDR write burst end self.end = Signal() # DDR mask of data to write (select which bytes will be written) self.mask = VectSignal(self.DATA_WIDTH // 8) # DDR write enable self.wren = Signal() # DDR driver is ready to accept write request self.rdy = Signal(masterDir=DIRECTION.IN)
def _declr(self): Axi_id._declr(self) self.found = Signal() self.addr = VectSignal(self.ADDR_WIDTH) if self.WAY_CNT > 1: self.way = VectSignal(log2ceil(self.WAY_CNT - 1)) if self.TAG_T is not None: self.tags = HObjList(HdlType_to_Interface().apply(self.TAG_T) for _ in range(self.WAY_CNT)) HandshakeSync._declr(self)
def _declr(self): if self.ID_WIDTH: self.id = VectSignal(self.ID_WIDTH) # rem is number of bits in last word which is valid - 1, # if rem == 0 it means all bytes are valid self.rem = VectSignal(log2ceil(self.DATA_WIDTH // 8)) if self.SHIFT_OPTIONS != (0, ): self.shift = VectSignal(log2ceil(len(self.SHIFT_OPTIONS))) if self.HAS_PROPAGATE_LAST: self.propagateLast = Signal() HandshakeSync._declr(self)
def _declr(self): self.ci = Signal() self.a = VectSignal(self.p_wordlength) self.b = VectSignal(self.p_wordlength) self.s = VectSignal(self.p_wordlength)._m() self.co = Signal()._m() # [wrong] manually instantiated child components (it is better to use HObjList) self.fa0 = FullAdder() self.fa1 = FullAdder() self.fa2 = FullAdder() self.fa3 = FullAdder()
def _declr_io(self): addClkRstn(self) with self._paramsShared(): self.dataIn = self.intfCls() self.dataOut = self.intfCls()._m() SIZE_W = log2ceil(self.DEPTH + 1 + 1) if self.EXPORT_SIZE: self.size = VectSignal(SIZE_W, signed=False)._m() if self.EXPORT_SPACE: self.space = VectSignal(SIZE_W, signed=False)._m()
def _declr(self): Handshaked._declr(self) self.addr = VectSignal(self.ADDR_WIDTH) # a flag which tells if the data was valid when the time of snapshot of the original register self.valid = Signal() self.orig_request_addr = VectSignal(self.ADDR_WIDTH) self.orig_request_id = VectSignal(self.ID_WIDTH) # a flag which tells if the request address equals the addres in orginal register during the time of the snapshot self.orig_request_addr_eq = Signal() # a flag which tells if this record is generated from input request or if this is a pipeline flush self.orig_request_valid = Signal()
class BoolToBitTest(Unit): def _declr(self): self.a = VectSignal(4) self.b = VectSignal(4) self.c = Signal()._m() def _impl(self): self.c(self.a._eq(self.b))
def _declr(self): self.a = VectSignal(4) self.b = VectSignal(4) self.c = Signal()._m()
def sig(name, width): a = VectSignal(width) a._name = name a._loadDeclarations() return a