def reinterpret_bits_to_hstruct(val, hStructT): """ Reinterpret signal of type Bits to signal of type HStruct """ container = HdlType_to_Interface(hStructT) container._loadDeclarations() offset = 0 for f in hStructT.fields: t = f.dtype width = t.bit_length() if f.name is not None: v = val[(width + offset):offset] v = v._reinterpret_cast(t) current = getattr(container, f.name) if isinstance(v, InterfaceBase): transfer_signals(v, current) elif isinstance(v, HObjList): raise NotImplementedError() elif isinstance(v, (RtlSignal, HValue)): current._sig = v else: raise NotImplementedError() offset += width return container
def _sig( self, name: str, dtype: HdlType = BIT, def_val: Union[int, None, dict, list] = None, nop_val: Union[int, None, dict, list, "NOT_SPECIFIED"] = NOT_SPECIFIED ) -> RtlSignal: """ Create signal in this unit :see: :func:`hwt.synthesizer.rtlLevel.netlist.RtlNetlist.sig` """ if isinstance(dtype, HStruct): container = HdlType_to_Interface().apply(dtype) _loadDeclarations(container, name) _instanciate_signals( container, None, None, def_val, nop_val, lambda name, dtype, clk, rst, def_val, nop_val: self._sig( name, dtype, def_val=def_val, nop_val=nop_val)) container._parent = self return container else: # primitive data type signal return self._ctx.sig(name, dtype=dtype, def_val=def_val, nop_val=nop_val)
def _declr(self): self.addr = VectSignal(self.MAIN_STATE_INDEX_WIDTH) if self.MAIN_STATE_T is not None: self.data = HdlType_to_Interface().apply(self.MAIN_STATE_T) if self.TRANSACTION_STATE_T is not None: self.transaction_state = HdlType_to_Interface().apply( self.TRANSACTION_STATE_T) HandshakeSync._declr(self)
def _reg(self, name: str, dtype: HdlType = BIT, def_val: Union[int, None, dict, list] = None, clk: Union[RtlSignalBase, None, Tuple[RtlSignalBase, OpDefinition]] = None, rst: Optional[RtlSignalBase] = None) -> RtlSyncSignal: """ Create RTL FF register in this unit :param def_val: s default value of this register, if this value is specified reset signal of this component is used to generate a reset logic :param clk: optional clock signal specification, (signal or tuple(signal, edge type (AllOps.RISING_EDGE/FALLING_EDGE))) :param rst: optional reset signal specification :note: rst/rst_n resolution is done from signal type, if it is negated type the reset signal is interpreted as rst_n :note: if clk or rst is not specified default signal from parent unit instance will be used """ if clk is None: clk = getClk(self) if def_val is None: # if no value is specified reset is not required rst = None elif rst is None: rst = getRst(self) if isinstance(dtype, HStruct): container = HdlType_to_Interface(dtype) container._loadDeclarations() flattened_def_val = {} _flatten_map(TypePath(), def_val, flattened_def_val) for path, intf in container._fieldsToInterfaces.items(): if isinstance(intf, Signal): _def_val = flattened_def_val.get(path, None) intf._sig = self._reg( "%s_%s" % (name, intf._getFullName(separator_getter=lambda x: "_")), intf._dtype, def_val=_def_val) return container elif isinstance(dtype, HArray): raise NotImplementedError() return self._ctx.sig(name, dtype=dtype, clk=clk, syncRst=rst, def_val=def_val)
def _reg(self, name: str, dtype: HdlType = BIT, def_val: Union[int, None, dict, list] = None, clk: Union[RtlSignalBase, None, Tuple[RtlSignalBase, OpDefinition]] = None, rst: Optional[RtlSignalBase] = None) -> RtlSyncSignal: """ Create RTL FF register in this unit :param def_val: s default value of this register, if this value is specified reset signal of this component is used to generate a reset logic :param clk: optional clock signal specification, (signal or tuple(signal, edge type (AllOps.RISING_EDGE/FALLING_EDGE))) :param rst: optional reset signal specification :note: rst/rst_n resolution is done from signal type, if it is negated type the reset signal is interpreted as rst_n :note: if clk or rst is not specified default signal from parent unit instance will be used """ if clk is None: clk = getClk(self) if def_val is None: # if no value is specified reset is not required rst = None elif rst is None: rst = getRst(self) if isinstance(dtype, (HStruct, HArray)): container = HdlType_to_Interface().apply(dtype) _loadDeclarations(container, name) _instanciate_signals( container, clk, rst, def_val, NOT_SPECIFIED, lambda name, dtype, clk, rst, def_val, nop_val: self._reg( name, dtype, def_val=def_val, clk=clk, rst=rst)) container._parent = self return container else: # primitive data type signal return self._ctx.sig(name, dtype=dtype, clk=clk, syncRst=rst, def_val=def_val)
def _declr(self): Axi_id._declr(self) self.found = Signal() self.addr = VectSignal(self.ADDR_WIDTH) if self.WAY_CNT > 1: self.way = VectSignal(log2ceil(self.WAY_CNT - 1)) if self.TAG_T is not None: self.tags = HObjList(HdlType_to_Interface().apply(self.TAG_T) for _ in range(self.WAY_CNT)) HandshakeSync._declr(self)
def _declr(self): assert self.T is not None self.data = HdlType_to_Interface().apply(self.T) HandshakeSync._declr(self)
def _declr(self): self.a = HdlType_to_Interface().apply(self.t) self.b = HdlType_to_Interface().apply(self.t) self.a_eq_b_out = Signal()._m() self.a_ne_b_out = Signal()._m()