def test_withStops(self): u = self.u u.a_en._ag.data.extend([1, 0, 0, 1]) u.b_en._ag.data.extend([1, 1, 0, 0, 1]) self.runSim(90 * Time.ns) self.assertSequenceEqual([1, 1, 0, 0, 1, 1, 1, 1], agInts(u.eq)) self.assertSequenceEqual(eightZeros, agInts(u.gt)) self.assertSequenceEqual([0, 0, 1, 1, 0, 0, 0, 0], agInts(u.lt)) self.assertSequenceEqual([0, 0, 1, 1, 0, 0, 0, 0], agInts(u.ne))
def test_aEnable(self): u = self.u u.a_en._ag.data.append(1) u.b_en._ag.data.append(0) self.runSim(90 * Time.ns) self.assertSequenceEqual([1, 0, 0, 0, 0, 0, 0, 0], agInts(u.eq)) self.assertSequenceEqual([0, 1, 1, 1, 1, 1, 1, 1], agInts(u.gt)) self.assertSequenceEqual(eightZeros, agInts(u.lt)) self.assertSequenceEqual([0, 1, 1, 1, 1, 1, 1, 1], agInts(u.ne))
def test_nonValid(self): u = self.u u.a_en._ag.data.append(None) u.b_en._ag.data.append(None) self.runSim(90 * Time.ns) self.assertSequenceEqual([1, None, None, None, None, None, None, None], agInts(u.eq)) self.assertSequenceEqual([0, None, None, None, None, None, None, None], agInts(u.gt)) self.assertSequenceEqual([0, None, None, None, None, None, None, None], agInts(u.lt)) self.assertSequenceEqual([0, None, None, None, None, None, None, None], agInts(u.ne))
def test_nothingEnable(self): u = self.u u.a_en._ag.data.append(0) u.b_en._ag.data.append(0) self.runSim(90 * Time.ns) self.assertSequenceEqual(eightOnes, agInts(u.eq)) self.assertSequenceEqual(eightZeros, agInts(u.gt)) self.assertSequenceEqual(eightZeros, agInts(u.lt)) self.assertSequenceEqual(eightZeros, agInts(u.ne))
def test_SimpleIfStatement(self): u = SimpleIfStatement() self.prepareUnit(u) u.a._ag.data.extend([1, 1, 1, 0, 0, 0, 0, 0]) u.b._ag.data.extend([0, 1, None, 0, 1, None, 1, 0]) u.c._ag.data.extend([0, 0, 0, 0, 1, 0, 0, 0]) self.runSim(80 * Time.ns) self.assertSequenceEqual([0, 1, None, 0, 1, None, 0, 0], agInts(u.d))
def test_sync_allData(self): self.setUpSync() u = self.u u.addr_in._ag.data.extend([0, 1, 2, 3, None, 3, 2, 1]) u.addr_out._ag.data.extend([None, 0, 1, 2, 3, None, 0, 1]) u.din._ag.data.extend([10, 11, 12, 13, 14, 15, 16, 17]) self.runSim(80 * Time.ns) self.assertSequenceEqual(valuesToInts([v for v in self.model.ram_data._val]), [None, 17, 16, 15]) self.assertSequenceEqual(agInts(u.dout), [None, None, 10, 11, 12, 13, None, None])
def test_sync_allData(self): self.setUpSync() u = self.u u.addr_in._ag.data.extend([0, 1, 2, 3, None, 3, 2, 1]) u.addr_out._ag.data.extend([None, 0, 1, 2, 3, None, 0, 1]) u.din._ag.data.extend([10, 11, 12, 13, 14, 15, 16, 17]) self.runSim(80 * Time.ns) self.assertSequenceEqual( valuesToInts([v for v in self.model.ram_data._val]), [None, 17, 16, 15]) self.assertSequenceEqual(agInts(u.dout), [None, None, 10, 11, 12, 13, None, None])