def asQuartusTcl(self, buff: List[str], version: str, component: Component,
packager: IpPackager, thisIf: Interface):
self.quartus_tcl_add_interface(buff, thisIf, packager)
name = packager.getInterfacePhysicalName(thisIf)
# self.quartus_prop("associatedClock", clock)
self.quartus_prop(buff, name, "synchronousEdges", "DEASSERT")
self.quartus_add_interface_port(buff, name, thisIf, "reset", packager)
clk = thisIf._getAssociatedClk()
if clk is not None:
self.quartus_prop(buff,
name,
"associatedClock",
packager.getInterfacePhysicalName(clk),
escapeStr=False)
def asQuartusTcl(self, buff: List[str], version: str, component,
entity: Entity, allInterfaces: List[Interface],
thisIf: Interface):
"""
Add interface to Quartus tcl
:param buff: line buffer for output
:param version: Quartus version
:param intfName: name of top interface
:param component: component object from ipcore generator
:param entity: Entity instance of top unit
:param allInterfaces: list of all interfaces of top unit
:param thisIf: interface to add into Quartus TCL
"""
name = getSignalName(thisIf)
self.quartus_tcl_add_interface(buff, thisIf)
clk = thisIf._getAssociatedClk()
if clk is not None:
self.quartus_prop(buff,
name,
"associatedClock",
clk._sigInside.name,
escapeStr=False)
rst = thisIf._getAssociatedRst()
if rst is not None:
self.quartus_prop(buff,
name,
"associatedReset",
rst._sigInside.name,
escapeStr=False)
m = self.get_quartus_map()
if m:
intfMapOrName = m
else:
intfMapOrName = thisIf.name
self._asQuartusTcl(buff, version, name, component, entity,
allInterfaces, thisIf, intfMapOrName)