def mkRegisterMap(u, modelCls): addrProbe = AddressSpaceProbe(u.cntrlBus, lambda intf: intf.ar.addr) self.regs = AxiLiteMemSpaceMaster(u.cntrlBus, addrProbe.discovered)
def mkRegisterMap(self, u): self.addrProbe = AddressSpaceProbe(u.bus, addrGetter) self.regs = AxiLiteMemSpaceMaster(u.bus, self.addrProbe.discovered)
def mkRegisterMap(self, u, modelCls): bus = u.cntrl self.addrProbe = AddressSpaceProbe(bus, addrGetter) self.regs = AxiLiteMemSpaceMaster(bus, self.addrProbe.discovered)
def mkRegisterMap(self, u, modelCls): self.addrProbe = AddressSpaceProbe(u.bus, addrGetter) self.regs = BramPortSimMemSpaceMaster(u.bus, self.addrProbe.discovered)
def mkRegisterMap(self, u): self.addrProbe = AddressSpaceProbe(u.bus, addrGetter) self.regs = IPFISimMaster(u.bus, self.addrProbe.discovered)
def mkRegisterMap(cls, u): cls.addrProbe = AddressSpaceProbe(u.cntrl, addrGetter) cls.regs = AxiLiteMemSpaceMaster(u.cntrl, cls.addrProbe.discovered)