def _declr(self):
assert self.CACHE_LINE_CNT > 0, self.CACHE_LINE_CNT
assert self.WAY_CNT > 0, self.WAY_CNT
assert self.CACHE_LINE_CNT % self.WAY_CNT == 0, (self.CACHE_LINE_CNT,
self.WAY_CNT)
self._compupte_tag_index_offset_widths()
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.m = Axi4()._m()
rc = self.read_cancel = AddrHs()._m()
rc.ID_WIDTH = 0
self.tag_array = AxiCacheTagArray()
self.lru_array = AxiCacheLruArray()
for a in [self.tag_array, self.lru_array]:
a.PORT_CNT = 2 # r+w
# self.flush = HandshakeSync()
# self.init = HandshakeSync()
data_array = self.data_array = RamSingleClock()
data_array.MAX_BLOCK_DATA_WIDTH = self.MAX_BLOCK_DATA_WIDTH
data_array.DATA_WIDTH = self.DATA_WIDTH
data_array.ADDR_WIDTH = log2ceil(
self.CACHE_LINE_CNT *
ceil(self.CACHE_LINE_SIZE * 8 / self.DATA_WIDTH))
data_array.PORT_CNT = (READ, WRITE)
data_array.HAS_BE = True
def _config(self):
# number of items in main array is resolved from ADDR_WIDTH and size of STATE_T
# number of concurent thread is resolved as 2**ID_WIDTH
self.MAIN_STATE_T = Param(uint32_t)
self.TRANSACTION_STATE_T = Param(uint8_t)
self.PIPELINE_CONFIG = Param(
OutOfOrderCummulativeOpPipelineConfig.new_config(
WRITE_HISTORY_SIZE=4 + 1)
)
Axi4._config(self)
def _declr(self) -> None:
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.ram = RamSingleClock()
self.ram.ADDR_WIDTH = self.ADDR_WIDTH - log2ceil(self.DATA_WIDTH //
8 - 1)
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl._replaceParam(cntrl.ADDR_WIDTH, self.CNTRL_AW)
cntrl._replaceParam(cntrl.DATA_WIDTH, self.DATA_WIDTH)
regs.ADDR_WIDTH.set(self.CNTRL_AW)
regs.DATA_WIDTH.set(self.DATA_WIDTH)
def _declr(self):
AxiWriteAggregatorWriteDispatcher.precompute_constants(self)
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.m = Axi4()._m()
if self.BUS_WORDS_IN_CACHE_LINE > 1:
fb = AxiSFifoCopy(Axi4_r)
fb.DEPTH = 2 * self.BUS_WORDS_IN_CACHE_LINE
else:
fb = AxiSRegCopy(Axi4_r)
self.frame_buff = fb
ac = self.addr_cam = CamMultiPort()
ac.MATCH_PORT_CNT = 1
ac.ITEMS = 2**self.ID_WIDTH
ac.USE_VLD_BIT = False
ac.KEY_WIDTH = self.CACHE_LINE_ADDR_WIDTH
for i in [self.s, self.m]:
i.HAS_W = False
def _declr(self):
with self._paramsShared():
addClkRstn(self)
self.axi = Axi4()._m()
self.axi.HAS_R = False
self.dataIn = Handshaked()
cntrl = self.cntrlBus = Axi4Lite()
regs = self.regsConventor = AxiLiteEndpoint(self.REGISTER_MAP)
cntrl.ADDR_WIDTH = self.CNTRL_AW
cntrl.DATA_WIDTH = self.DATA_WIDTH
regs.ADDR_WIDTH = self.CNTRL_AW
regs.DATA_WIDTH = self.DATA_WIDTH
def _declr(self) -> None:
addClkRstn(self)
with self._paramsShared():
self.s = Axi4()
self.m = AvalonMM()._m()
# a tmp buffer for sizes of read transactions to generate ax.r.last
f = self.r_size_fifo = HandshakedFifo(IdLenHs)
f.DEPTH = self.R_DATA_FIFO_DEPTH
f.LEN_WIDTH = self.s.LEN_WIDTH
f.ID_WIDTH = self.ID_WIDTH
if self.MAX_BURST != 2 ** (self.s.LEN_WIDTH + 1):
raise NotImplementedError(self.MAX_BURST, (2 ** self.s.LEN_WIDTH + 1))
def _declr(self):
addClkRstn(self)
AxiWriteAggregatorWriteDispatcher.precompute_constants(self)
with self._paramsShared():
self.w = w = AxiWriteAggregatorWriteIntf()
self.w_in_reg = w_in_reg = HandshakedReg(
AxiWriteAggregatorWriteTmpIntf)
w.ADDR_WIDTH = w_in_reg.ADDR_WIDTH = self.CACHE_LINE_ADDR_WIDTH
w.DATA_WIDTH = w_in_reg.DATA_WIDTH = self.CACHE_LINE_SIZE * 8
self.m = axi = Axi4()._m()
axi.HAS_R = False
self.write_dispatch = AxiWriteAggregatorWriteDispatcher()
self.ooo_fifo = of = FifoOutOfOrderReadFiltered()
of.ITEMS = w_in_reg.ITEMS = 2**self.ID_WIDTH
of.KEY_WIDTH = self.CACHE_LINE_ADDR_WIDTH
self.data_ram = self._declr_data_ram()
def _declr(self):
addClkRstn(self)
self._init_constants()
with self._paramsShared():
self.m = Axi4()._m()
self.ooo_fifo = FifoOutOfOrderRead()
self.ooo_fifo.ITEMS = 2 ** self.ID_WIDTH
sa = self.state_array = RamSingleClock()
sa.PORT_CNT = (WRITE, READ)
sa.ADDR_WIDTH = self.ID_WIDTH
TRANSACTION_STATE_T = self.TRANSACTION_STATE_T
# address + TRANSACTION_STATE_T
sa.DATA_WIDTH = self.MAIN_STATE_INDEX_WIDTH + (
0 if TRANSACTION_STATE_T is None else
TRANSACTION_STATE_T.bit_length()
)
self._declr_io()
def _declr(self):
addClkRstn(self)
self.precompute_constants()
# port to pull data from memory
d = self.data = BramPort_withReadMask_withoutClk()._m()
d.DATA_WIDTH = self.DATA_WIDTH
d.ADDR_WIDTH = self.DATA_RAM_INDEX_WIDTH
d.HAS_W = False
d.HAS_BE = self.DATA_WIDTH > 8
# begin the read of the item
wl = self.read_execute = IndexKeyHs()
wl.KEY_WIDTH = self.CACHE_LINE_ADDR_WIDTH
wl.INDEX_WIDTH = self.ID_WIDTH
# confirm that the item was read and the item in fifo is ready to be used again
pc = self.read_confirm = Handshaked()._m()
pc.DATA_WIDTH = self.ID_WIDTH
# bus to write items to
with self._paramsShared():
self.m = Axi4()._m()
self.m.HAS_R = False
def _declr(self):
self.a = Axi4()
self.b = Axi4()._m()
def _config(self):
Axi4._config(self)
self.SNOOP_ADDR_WIDTH = Param(32)
self.SNOOP_DATA_WIDTH = Param(32)
def _config(self) -> None:
Axi4._config(self)
self.DATA_WIDTH = 512
self.ADDR_WIDTH = 10
def _config(self):
Axi4._config(self)
self.WAY_CNT = Param(4)
self.MAX_BLOCK_DATA_WIDTH = Param(None)
CacheAddrTypeConfig._config(self)
def _config(self):
Axi4._config(self)
self.CACHE_LINE_SIZE = Param(64) # [B]
def connect_w(self, s_w: AddrDataHs, axi: Axi4, w_cntr: RtlSignal,
CNTR_MAX: int, in_axi_t: HStruct):
def axi_w_deparser_parametrization(u: AxiS_frameDeparser):
# [TODO] specify _frames or maxFrameLen if required (AXI3 16beats, AXI4 256)
u.DATA_WIDTH = axi.DATA_WIDTH
u.ID_WIDTH = 0
# component to create a axi-stream like packet from AddrDataHs write data
w_builder, w_in = AxiSBuilder.deparse(self, in_axi_t, Axi4.W_CLS,
axi_w_deparser_parametrization)
w_in = w_in.data
self.addr_defaults(axi.aw)
if self.data_words_in_axi_word <= 1:
self.connect_addr(s_w.addr, axi.aw.addr)
w_in.data(s_w.data, fit=True)
aw_sn = StreamNode([s_w], [axi.aw, w_in])
else:
addr, sub_addr = self.split_subaddr(s_w.addr)
self.connect_addr(addr, axi.aw.addr)
w_in._select.data(sub_addr)
# sel = HsBuilder(self, w_in._select, master_to_slave=False)\
# .buff(self.MAX_TRANS_OVERLAP).end
# sel.data(sub_addr)
w_reg = HandshakedReg(Handshaked)
w_reg.DATA_WIDTH = s_w.DATA_WIDTH
self.w_data_reg = w_reg
w_reg.dataIn.data(s_w.data)
aw_sn = StreamNode([s_w], [axi.aw, w_reg.dataIn, w_in._select])
data_items = [
getattr(w_in, f"data{i:d}").data
for i in range(self.data_words_in_axi_word)
]
for w in data_items:
w.vld(w_reg.dataOut.vld)
w.data(w_reg.dataOut.data)
# ready is not important because it is part of ._select.rd
w_reg.dataOut.rd(Or(*[d.rd for d in data_items]))
w_start_en = w_cntr != CNTR_MAX
aw_sn.sync(w_start_en)
# s_w.rd(win.rd)
# axi.aw.valid(s_w.vld & w_start_en & ~waiting_for_w_data & win.rd)
# win.vld(s_w.vld & w_start_en & axi.aw.ready)
if hasattr(axi.w, "id"):
# axi3
axi.w(w_builder.end, exclude={axi.w.id})
axi.w.id(0)
else:
# axi4
axi.w(w_builder.end)
If(axi.aw.ready & axi.aw.valid,
If(~axi.b.valid, w_cntr(w_cntr + 1))).Elif(axi.b.valid,
w_cntr(w_cntr - 1))
axi.b.ready(1)