def dispatch_addr(self, id_to_use: RtlSignal, addr: RtlSignal, a: Axi4_addr): """ * if there is a valid item in buffer dispatch read request """ a_ld = self._sig("a_ld") a_tmp = self._reg("ar_tmp", HStruct( (a.id._dtype, "id"), (addr._dtype, "addr"), (BIT, "vld"), ), def_val={"vld": 0}) If(a_ld, a_tmp.id(id_to_use), a_tmp.addr(addr), a_tmp.vld(1)).Else(a_tmp.vld(a_tmp.vld & ~a.ready)) a.id(a_tmp.id) a.addr(Concat(a_tmp.addr, Bits(self.CACHE_LINE_OFFSET_BITS).from_py(0))) a.len(self.BUS_WORDS_IN_CACHE_LINE - 1) a.burst(BURST_INCR) a.prot(PROT_DEFAULT) a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8)) a.lock(LOCK_DEFAULT) a.cache(CACHE_DEFAULT) a.qos(QOS_DEFAULT) a.valid(a_tmp.vld) return a_ld
def axiAddrDefaults(self, a: Axi4_addr): a.burst(BURST_INCR) a.cache(CACHE_DEFAULT) a.lock(LOCK_DEFAULT) a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8)) a.prot(PROT_DEFAULT) a.qos(QOS_DEFAULT)
def _axi_addr_defaults(self, a: Axi4_addr, word_cnt: int): """ Set default values for AXI address channel signals """ a.len(word_cnt - 1) a.burst(BURST_INCR) a.prot(PROT_DEFAULT) a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8)) a.lock(LOCK_DEFAULT) a.cache(CACHE_DEFAULT) a.qos(QOS_DEFAULT)
def addr_defaults(self, a: Axi4_addr): axi = self.m a.id(0) a.burst(BURST_INCR) a.cache(CACHE_DEFAULT) words = ceil(self.S_DATA_WIDTH / axi.DATA_WIDTH) a.len(words - 1) a.lock(LOCK_DEFAULT) a.size(BYTES_IN_TRANS(axi.DATA_WIDTH // 8)) a.prot(PROT_DEFAULT) if hasattr(a, "qos"): # axi4 a.qos(QOS_DEFAULT)