def test_read_3B(self): with tempfile.TemporaryDirectory(prefix='glx_test') as tdir: bin_3b = spikeglx._mock_spikeglx_file( Path(tdir).joinpath('sample3B_g0_t0.imec1.ap.bin'), self.workdir / 'sample3B_g0_t0.imec1.ap.meta', ns=32, nc=385, sync_depth=16) self.assert_read_glx(bin_3b)
def test_read_nidq(self): # nidq has 1 analog and 1 digital sync channels self.tdir = tempfile.TemporaryDirectory(prefix='glx_test') nidq = spikeglx._mock_spikeglx_file(self.tdir.name, self.workdir / 'sample3B_g0_t0.nidq.meta', ns=32, nc=2, sync_depth=8) self.assert_read_glx(nidq)
def test_read_nidq(self): # nidq has 1 analog and 1 digital sync channels with tempfile.TemporaryDirectory(prefix='glx_test') as tdir: int2volts = 5 / 32768 nidq = spikeglx._mock_spikeglx_file( Path(tdir).joinpath('sample3B_g0_t0.nidq.bin'), self.workdir / 'sample3B_g0_t0.nidq.meta', ns=32, nc=2, sync_depth=8, int2volts=int2volts) self.assert_read_glx(nidq)
def test_read_3A(self): self.tdir = tempfile.TemporaryDirectory(prefix='glx_test') bin_3a = spikeglx._mock_spikeglx_file( Path(self.tdir.name).joinpath('sample3A_g0_t0.imec.ap.bin'), self.workdir / 'sample3A_g0_t0.imec.ap.meta', ns=32, nc=385, sync_depth=16) self.assert_read_glx(bin_3a)
def setUp(self): self._tempdir = tempfile.TemporaryDirectory() # self.addClassCleanup(self._tempdir.cleanup) # py3.8 self.workdir = Path(self._tempdir.name) file_meta = Path(__file__).parent.joinpath('fixtures', 'io', 'spikeglx', 'sample3A_short_g0_t0.imec.ap.meta') self.file_bin = spikeglx._mock_spikeglx_file( self.workdir.joinpath('sample3A_short_g0_t0.imec.ap.bin'), file_meta, ns=76104, nc=385, sync_depth=16, random=True)['bin_file'] self.sr = spikeglx.Reader(self.file_bin)
def test_check_ephys_file(self): self.tdir = tempfile.TemporaryDirectory(prefix='glx_test') self.addCleanup(self.tdir.cleanup) bin_3b = spikeglx._mock_spikeglx_file( Path(self.tdir.name).joinpath('sample3B_g0_t0.imec1.ap.bin'), self.workdir / 'sample3B_g0_t0.imec1.ap.meta', ns=32, nc=385, sync_depth=16) self.assertEqual(hashfile.md5(bin_3b['bin_file']), "207ba1666b866a091e5bb8b26d19733f") self.assertEqual(hashfile.sha1(bin_3b['bin_file']), '1bf3219c35dea15409576f6764dd9152c3f8a89c') sr = spikeglx.Reader(bin_3b['bin_file']) self.assertTrue(sr.verify_hash())
def test_read_corrupt(self): # nidq has 1 analog and 1 digital sync channels self.tdir = tempfile.TemporaryDirectory(prefix='glx_test') int2volts = 5 / 32768 nidq = spikeglx._mock_spikeglx_file( Path(self.tdir.name).joinpath('sample3B_g0_t0.nidq.bin'), self.workdir / 'sample3B_g0_t0.nidq.meta', ns=32, nc=2, sync_depth=8, int2volts=int2volts, corrupt=True) self.assert_read_glx(nidq)
def sync_gen(self, fn, ns, nc, sync_depth): # nidq has 1 analog and 1 digital sync channels with tempfile.TemporaryDirectory() as tdir: ses_path = Path(tdir).joinpath('raw_ephys_data') ses_path.mkdir(parents=True, exist_ok=True) nidq = spikeglx._mock_spikeglx_file(ses_path, self.workdir / fn, ns=ns, nc=nc, sync_depth=sync_depth) syncs = ephys_fpga.extract_sync(tdir, save=True) self.assertTrue( np.all(syncs[0].channels[slice(0, None, 2)] == np.arange( 0, nidq['sync_depth']))) with self.assertLogs(level='INFO') as log: syncs = ephys_fpga.extract_sync(tdir) self.assertEqual(len(log.output), 1) self.assertIn('spike GLX sync found', log.output[0])
def test_read_3B(self): self.tdir = tempfile.TemporaryDirectory(prefix='glx_test') bin_3b = spikeglx._mock_spikeglx_file(self.tdir.name, self.workdir / 'sample3B_g0_t0.imec1.ap.meta', ns=32, nc=385, sync_depth=16) self.assert_read_glx(bin_3b)