def set_init(self):
bar_spec = ptxILA.barSpec()
self.a_is_bar = (self.opcode_a == bar_spec.BAR_OPCODE)
#self.a_is_bar = (self.pc_a == 20)
self.a_previous_bar = self.model.bit('a_previous_bar')
self.model.set_next('a_previous_bar', self.a_is_bar)
self.a_cross_bar_flag = self.model.bit('a_cross_bar_flag')
self.model.set_next(
'a_cross_bar_flag',
ila.ite((self.a_is_bar == ila.bool(False)) &
(self.a_previous_bar == ila.bool(True)), ila.bool(True),
self.a_cross_bar_flag))
self.b_is_bar = (self.opcode_b == bar_spec.BAR_OPCODE)
self.b_come_to_bar_flag = self.model.bit('b_come_to_bar_flag')
self.model.set_next(
'b_come_to_bar_flag',
ila.ite(self.b_is_bar, ila.bool(True), self.b_come_to_bar_flag))
self.predicate_one = self.model.bit('predicate_one')
self.model.set_next('predicate_one', (~self.a_cross_bar_flag) |
(self.b_come_to_bar_flag))
self.model.set_init('a_previous_bar', self.model.bool(False))
self.model.set_init('a_cross_bar_flag', self.model.bool(False))
self.model.set_init('b_come_to_bar_flag', self.model.bool(False))
self.model.set_init('predicate_one', self.model.bool(True))
golden = ila.Abstraction('golden')
g_prop = golden.bit('prop')
golden.set_next('prop', golden.bool(True))
golden.set_init('prop', golden.bool(True))
ila.bmc(30, self.model, self.predicate_one, 1, golden, g_prop)
def createLog(self):
ld_set_file = 'ld_set'
ld_set_obj = open(ld_set_file)
ld_set = pickle.load(ld_set_obj)
ld_set_obj.close()
st_set_file = 'st_set'
st_set_obj = open(st_set_file)
st_set = pickle.load(st_set_obj)
st_set_obj.close()
for pc in ld_set.keys():
reg_name = ld_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (0)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (0))
else:
operands[i] = ila.const(int(operand), reg_len)
log_reg = self.model.reg(reg_name + '_log_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.log_registers.append(log_reg)
log_reg_next = operands[0]
for i in range(len(operands)):
log_reg_next = log_reg_next + operands[i]
self.model.set_next(
reg_name + '_log_%d' % (pc),
ila.ite(self.pc_list[0] == (pc), log_reg_next, log_reg))
for pc in st_set.keys():
reg_name = st_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (0)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (0))
else:
operands[i] = ila.const(int(operand), reg_len)
log_reg = self.model.reg(reg_name + '_log_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.log_registers.append(log_reg)
log_reg_next = operands[0]
for i in range(len(operands)):
log_reg_next = log_reg_next + operands[i]
self.model.set_next(
reg_name + '_log_%d' % (pc),
ila.ite(self.pc_list[0] == (pc), log_reg_next, log_reg))
def PTEcheck(inst, mstatus, Priv, pte, takeInt):
opcode = inst[6:0]
MXR = mstatus[19]
PUM = mstatus[18]
MPRV = mstatus[17]
MPP = mstatus[12:11]
effectPriv = ila.ite((Priv == MACHINE) & (MPRV == 1), MPP, Priv)
disallowUser = (effectPriv != USER) & (PUM == 1)
allowXasR = (effectPriv == MACHINE) & (MXR == 1)
pte_V = pte[0]
pte_R = pte[1]
pte_W = pte[2]
pte_X = pte[3]
pte_U = pte[4]
pte_G = pte[5]
pte_A = pte[6]
pte_D = pte[7]
nonleaf_pte = pte_V & (~pte_R) & (~pte_X)
fault_condition = (~takeInt) & (
(pte_V == 0) | ((pte_R == 0) & (pte_W == 1)) | ((opcode == STORE) &
(pte_W == 0)) |
((opcode == LOAD) & (ila.ite(allowXasR, pte_X | pte_R, pte_R) == 0)) |
((pte_U == 1) & disallowUser) | ((pte_U == 0) & (effectPriv != USER)))
return fault_condition
def test4():
I1 = ila.Abstraction('a')
inp1 = I1.inp('inp', 1)
r1 = I1.reg('r1', 5)
r1a = I1.reg('ra', 5)
I1.decode_exprs = [inp1 == 1, inp1 == 0]
uI1 = I1.add_microabstraction("mic", (r1 != 0))
I1.set_next('r1', ila.ite(inp1 == 1, I1.const(1, 5), I1.const(0, 5)))
I1.set_next('ra', r1a)
ur1 = uI1.reg('ur1', 5)
r1p = uI1.getreg('r1')
uI1.set_init('ur1', uI1.const(0, 5))
uI1.set_next('ur1', ur1 + 1)
ura1 = uI1.getreg('ra')
uI1.set_next('ra', ura1 - 1)
uI1.set_next('r1', ila.ite(ura1 == 1, I1.const(0, 5), I1.const(1, 5)))
#######################
I2 = ila.Abstraction('b')
inp2 = I2.inp('inp', 1)
r2 = I2.reg('r1', 5)
r2a = I2.reg('ra', 5)
I2.decode_exprs = [inp2 == 1, inp2 == 0]
uI2 = I2.add_microabstraction("mic", (r2 != 0))
I2.set_next('r1', ila.ite(inp2 == 1, I2.const(1, 5), I2.const(0, 5)))
I2.set_next('ra', r2a)
ur2 = uI2.reg('ur1', 5)
r2p = uI2.getreg('r1')
uI2.set_init('ur1', uI2.const(0, 5))
uI2.set_next('ur1', ur2 + 1)
ura2 = uI2.getreg('ra')
uI2.set_next('ra', uI2.getreg('ra') - 1)
uI2.set_next('r1', ila.ite(ura2 == 1, I2.const(0, 5), I2.const(1, 5)))
print 'simple signature test:'
print ila.eqcheckSimple(I1, I2)
print 'full test'
u1 = I1.newUnroller(uI1, False)
u1.unrollTo(4)
u2 = I2.newUnroller(uI2, False)
u2.unrollTo(4)
inductiveAssumpt = [(1, "r1", "r1"), (1, "ra", "ra"), (1, "ur1", "ur1")]
print ila.eqcheck(u1, u2, "r1", "r1", inductiveAssumpt)
print ila.eqcheck(u1, u2, "ra", "ra", inductiveAssumpt)
print ila.eqcheck(u1, u2, "ur1", "ur1", inductiveAssumpt)
def auz_ctz(self, data): counter = self.model.const(0b0, SCALAR_REG_BITS) flag = self.model.const(0b0, 1) for idx in xrange(SCALAR_REG_BITS)[::-1]: counter = ila.ite(flag == self.model.const(0b0, 1), ila.ite(data[idx] == self.model.const(0b0, 1), counter + 1, counter), counter) flag = ila.ite(flag == self.model.const(0b1, 1), flag, ila.ite(data[idx] == self.model.const(0b0, 1), flag, self.model.const(0b0, 1))) return counter
def aux_dest(self, opcode, src_list):
dest = None
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name == 'mov':
dest = src_list[0]
if opcode_name == 'and':
dest = src_list[0] & src_list[1]
if opcode_name == 'cvta':
dest = src_list[0]
if opcode_name == 'shr':
dest = ila.ashr(src_list[0], src_list[1])
if opcode_name == 'add':
dest = src_list[0] + src_list[1]
if opcode_name == 'sub':
dest = src_list[0] - src_list[1]
if opcode_name == 'mul':
opcode_width = opcode_split[1]
op_len = int(opcode_split[2][1:])
if opcode_width == 'wide':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest = src0 * src1
if opcode_name == 'setp':
opcode_cmp = opcode_split[1]
if opcode_cmp == 'ne':
dest = ila.ite(src_list[0] != src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'gt':
dest = ila.ite(src_list[0] > src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'lt':
dest = ila.ite(src_list[0] < src_list[1], self.pred_one,
self.pred_zero)
return dest
def set_next_state(self):
# reg next state
for state_name in self.next_state_dict.keys():
index = int(state_name[-1])
self.model.set_next(state_name, self.next_state_dict[state_name])
self.model.set_next('log_register', self.log_register_next)
self.model.set_next('check_register', self.check_register_next)
self.model.set_next('en_log_register', self.en_log_register_next)
self.model.set_next('en_check_register', self.en_check_register_next)
self.model.set_next('lsg_log_register', self.lsg_log_register_next)
self.model.set_next('lsg_check_register', self.lsg_check_register_next)
self.model.set_next(
'mflag_log_register',
ila.ite(self.mflag_log_register_next_cond, self.mutex_flag_list[0],
self.mflag_log_register))
self.model.set_next(
'mguard_log_register',
ila.ite(self.mflag_log_register_next_cond,
self.mutex_guard_list[0], self.mguard_log_register))
self.model.set_next(
'mflag_check_register',
ila.ite(self.mflag_check_register_next_cond,
self.mutex_flag_list[1], self.mflag_check_register))
self.model.set_next(
'mguard_check_register',
ila.ite(self.mflag_check_register_next_cond,
self.mutex_guard_list[1], self.mguard_check_register))
self.model.set_next('mutex_flag_0', self.mutex_flag_next_list[0])
self.model.set_next('mutex_flag_1', self.mutex_flag_next_list[1])
self.model.set_next('mutex_guard_0', self.mutex_guard_next_list[0])
self.model.set_next('mutex_guard_1', self.mutex_guard_next_list[1])
self.model.set_next('log_atom_flag_register',
self.log_atom_flag_register_next)
self.model.set_next('check_atom_flag_register',
self.check_atom_flag_register_next)
def U2b(gb):
m = gb.abst
FULL_T = gb.FULL_TRUE
FULL_F = gb.FULL_FALSE
EMPTY_T = gb.EMPTY_TRUE
EMPTY_F = gb.EMPTY_FALSE
############################ decode ###################################
decode = (gb.in_stream_empty == EMPTY_F) & \
(gb.LB2D_proc_x == gb.LB2D_proc_x_M) & \
((gb.slice_stream_full == FULL_F) | \
(gb.LB2D_proc_y < gb.LB2D_proc_size))
############################ next state functions #####################
# LB2D_proc_x
LB2D_proc_x_nxt = gb.LB2D_proc_x_1
gb.LB2D_proc_x_nxt = ila.ite(decode, LB2D_proc_x_nxt, gb.LB2D_proc_x_nxt)
# LB2D_proc_y
LB2D_proc_y_nxt = ila.ite(gb.LB2D_proc_y == gb.LB2D_proc_y_M,
gb.LB2D_proc_y_0,
gb.LB2D_proc_y + gb.LB2D_proc_y_1)
gb.LB2D_proc_y_nxt = ila.ite(decode, LB2D_proc_y_nxt, gb.LB2D_proc_y_nxt)
# LB2D_proc_w
LB2D_proc_w_nxt = ila.ite(gb.LB2D_proc_w == gb.LB2D_proc_w_M,
gb.LB2D_proc_w_0,
gb.LB2D_proc_w + gb.LB2D_proc_w_1)
gb.LB2D_proc_w_nxt = ila.ite(decode, LB2D_proc_w_nxt, gb.LB2D_proc_w_nxt)
def indexIntoSGPR(self, index, base_flag = False, SCC_flag = False, EXEC_flag = False):
SGPR = self.scalar_registers[0] #start from s0
for idxIter in xrange(1, SCALAR_REG_NUM_PER_WORK_GROUP):
SGPR = ila.ite(index == idxIter, self.scalar_registers[index], SGPR)
SGPR = ila.ite(base_flag, self.base_register_address, SGPR)
SGPR = ila.ite(SCC_flag, self.SCC, SGPR)
SGPR = ila.ite(EXEC_flag, self.EXEC, SGPR)
return SGPR
def getSlice(v, lowBits):
expr = \
ila.ite( lowBits == 0, ila.choice('lowbits_0',ext(v[7:0]), ext(v[15:0]), ext(v[23:0] ), v[31:0] ),
ila.ite( lowBits == 1, ila.choice('lowbits_1' , ext(v[15:8]), ext(v[23:8] ), ext(v[31:8] ) ),
ila.ite( lowBits == 2, ila.choice('lowbits_2' , ext(v[23:16]), ext(v[31:16]) ),
ila.ite( lowBits == 3, ext(v[31:24]) ,
v[31:0]
))))
return expr
def nextCondition(l0, l1, l2, l3, l4, default):
return ila.ite(
SumHiddenL0, l0,
ila.ite(
SumHiddenL1, l1,
ila.ite(
SumHiddenL2, l2,
ila.ite(SumHiddenL3, l3, ila.ite(SumHiddenL4, l4,
default)))))
def ptxSample(self):
instruction_map_file = 'instruction_map'
instruction_map_obj = open(instruction_map_file, 'r')
instruction_map = pickle.load(instruction_map_obj)
return ila.ite(
self.dest == 0,
ila.ite(self.opcode == instruction_map['mul.lo'],
self.sreg1 * self.sreg2, self.scalar_registers[0]),
self.scalar_registers[0])
def buildPrivInst(
self): # Should handle x0-x31 update, should not touch pc/csrs
riscv = self.riscv
inst = riscv.inst
opcode = riscv.opcode
funct12 = riscv.funct12
CSRRegs = riscv.CSRRegs
#--------------------
# CSR decomposition
#--------------------
status_SD = CSRRegs['mstatus'][XLEN - 1]
status_VM = CSRRegs['mstatus'][28:24]
status_MXR = CSRRegs['mstatus'][19]
status_PUM = CSRRegs['mstatus'][18]
status_MPRV = CSRRegs['mstatus'][17]
status_MPP = CSRRegs['mstatus'][12:11]
status_HPP = CSRRegs['mstatus'][10:9]
status_SPP = CSRRegs['mstatus'][8]
status_MPIE = CSRRegs['mstatus'][7]
status_HPIE = CSRRegs['mstatus'][6]
status_SPIE = CSRRegs['mstatus'][5]
status_UPIE = CSRRegs['mstatus'][4]
status_MIE = CSRRegs['mstatus'][3]
status_HIE = CSRRegs['mstatus'][2]
status_SIE = CSRRegs['mstatus'][1]
status_UIE = CSRRegs['mstatus'][0]
(csrRWExpr,csrRSExpr,csrRCExpr,csrIExpr,EcallExpr,EbrkExpr,TrapRetExp,SfenceVMExpr) \
= self.PrivDecode()
self.isTrapReturn = (inst == 0x10200073) | (inst == 0x30200073)
self.isMRET = inst == 0x30200073
self.isSRET = inst == 0x10200073
self.isEBreak = (opcode == RVEncoding.SYSTEM) & (funct12
== RVEncoding.EBREAK)
self.trapRetPC = ila.ite(self.isMRET, CSRRegs['mepc'], CSRRegs['sepc'])
self.trapRetPriv = ila.ite(
self.isMRET,
ila.ite(status_MPP == RVEncoding.HYPERVISOR,
const(RVEncoding.SUPERVISOR, 2), status_MPP),
ila.concat([b0, status_SPP]))
# gen CSR Inst Update List, add interrupt choice to the merge ones
csr_W_inst_update = {} # Indep CSRNAME-> update function
for csrName, CSRinf in riscv.CSRInfo.items():
### OPT-OUT ###
if CSRinf.parent is not None:
continue
old = CSRRegs[csrName]
csr_W_inst_update[csrName] = old
self.csr_W_inst_update = csr_W_inst_update
"""
def indexIntoVGPR(self, index, threadNo, VCC_flag = False):
VGPR = self.vector_registers[0][0]
for idxIter in xrange(1, VECTOR_REG_NUM_PER_WAVE_FRONT):
for thrdIter in xrange(1, VECTOR_THREAD):
VGPR = ila.ite((index == idxIter) & (threadNo == thrdIter),
self.vector_registers[index][threadNo], VGPR)
VGPR = ila.ite(VCC_flag, self.VCC, VGPR)
return VGPR
def perform_instruction(self, index, program_line, pc_target):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name != '@':
self.next_state_finished.append(program_line[1])
conj_pred = self.pred_gen(index, self.pred_map[self.current_pc])
if opcode_name == 'bar':
op_len = 0
else:
op_len = int(opcode_split[-1][1:])
src_list = []
for i in range(2, len(program_line)):
src_str = program_line[i]
src_components = re.split('\+', src_str)
for i in range(len(src_components)):
src_component = src_components[i]
src_components[i] = self.aux_imm(src_component, index,
op_len)
src_sum = src_components[0]
for i in range(1, len(src_components)):
src_sum = src_sum + src_components[0]
src_list.append(src_sum)
dest = self.aux_dest(program_line[0], src_list, index)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
current_next_state = self.next_state_dict[dest_str + '_%d' %
(index)]
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc,
ila.ite(conj_pred, dest, current_next_state),
current_next_state)
self.current_pc += 4
return
else:
conj_pred0 = self.pred_gen(0, self.pred_map[self.current_pc])
conj_pred1 = self.pred_gen(1, self.pred_map[self.current_pc])
opcode_jmp_dest = program_line[3]
opcode_jmp_target = pc_target[opcode_jmp_dest]
if (opcode_jmp_target > self.current_pc):
opcode_pred = conj_pred0 & conj_pred1
else:
opcode_pred = conj_pred0 | conj_pred1
pc_jmp = ila.ite(
opcode_pred,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
def create_data_race_element(self, access_set, pred_map, log):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (index)),
reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' %
(index))
else:
operands[i] = ila.const(int(operand), reg_len)
access_reg = self.model.reg(reg_name + '_%s_%d' % (suffix, pc),
instruction_format.LONG_REG_BITS)
if log:
self.log_registers.append(access_reg)
else:
self.check_registers.append(access_reg)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
self.model.set_next(
reg_name + '_%s_%d' % (suffix, pc),
ila.ite(self.pc_list[index] == (pc), access_reg_next,
access_reg))
en_access_reg = self.model.reg(
reg_name + '_en_%s_%d' % (suffix, pc), 1)
if log:
self.en_log_registers.append(en_access_reg)
else:
self.en_check_registers.append(en_access_reg)
en_access_reg_next = ila.const(0x1, 1)
pred_list = pred_map[pc]
for pred in pred_list:
pred_reg = self.model.getreg(pred + '_%d' % (index))
en_access_reg_next = ila.ite(pred_reg == ila.const(0x0, 1),
en_access_reg_next, en_access_reg)
self.model.set_next(
reg_name + '_en_%s_%d' % (suffix, pc),
ila.ite(self.pc_list[index] == pc, en_access_reg_next,
en_access_reg))
def instructionFetch(self):
self.instruction = ila.load(
self.mem, ila.zero_extend(self.pc[31:2], MEM_ADDRESS_BITS))
self.isBranch = (self.instruction[31:28] == self.model.const(
0b1111, 4))
self.branchOP = self.instruction[27:25]
self.branchOffsetA = self.instruction[24:5]
self.branchSrc = self.instruction[4:0]
self.branchOffsetB = self.instruction[24:0]
self.isRegReg = (self.instruction[31:29] == self.model.const(0b110, 3))
self.rrType = self.instruction[28:26]
self.rrOpcode = self.instruction[25:20]
self.rrSrc2 = self.instruction[19:15]
self.rrMask = self.instruction[14:10]
self.rrDest = self.instruction[9:5]
self.rrSrc1 = self.instruction[4:0]
self.isImmediate = (self.instruction[31] == self.model.const(0b0, 1))
self.immType = self.instruction[30:29]
self.immOpcode = self.instruction[28:24]
self.immA = ila.zero_extend(self.instruction[23:15], SCALAR_REG_BITS)
self.immB = ila.zero_extend(self.instruction[23:10], SCALAR_REG_BITS)
self.immCup = self.instruction[23:10]
self.immClow = self.instruction[4:0]
self.immDest = self.instruction[9:5]
self.immMask = self.instruction[14:10]
self.imm = ila.ite(
self.immType[1] == self.model.const(0b0, 1),
ila.zero_extend(self.immB, SCALAR_REG_BITS),
ila.ite(
self.immType == self.model.const(0b10, 2),
ila.zero_extend(ila.concat(self.immCup, self.immClow),
SCALAR_REG_BITS),
ila.ite(self.immType == self.model.const(0b11, 2),
ila.zero_extend(self.immA, SCALAR_REG_BITS),
ila.zero_extend(self.immA, SCALAR_REG_BITS))))
self.isMem = (self.instruction[31:30] == self.model.const(0b10, 2))
self.isLoad = self.instruction[29]
self.memOpcode = self.instruction[28:25]
self.memOffSetA = self.instruction[24:15]
self.memOffSetB = self.instruction[24:10]
self.memMask = self.instruction[14:10]
self.memDest = self.instruction[9:5]
self.memSrc = self.instruction[9:5]
self.memPtr = self.instruction[4:0]
self.memOffSet = ila.ite(
self.memOpcode == self.model.const(0b1000, 4),
ila.sign_extend(self.memOffSetA, SCALAR_REG_BITS),
ila.ite(self.memOpcode == self.model.const(0b1110, 4),
ila.sign_extend(self.memOffSetA, SCALAR_REG_BITS),
ila.sign_extend(self.memOffSetB, SCALAR_REG_BITS)))
self.isMask = (
((self.rrType == self.model.const(0b010, 3)) |
(self.rrType == self.model.const(0b101, 3))) & self.isRegReg
) #need rewrite
self.dest = self.instruction[9:5]
def readCSR(self,idx):
expr = const(0,XLEN)
for name, CSR in self.CSRInfo.items():
csrIdxName = name if CSR.parent is None else CSR.parent
if name == 'sip':
expr = ila.ite( CSR.addr == idx, CSRRegs['mip'] & CSRRegs['mideleg'], expr ) # delegatable will enter the next level
elif name == 'sie':
expr = ila.ite( CSR.addr == idx, CSRRegs['mie'] & CSRRegs['mideleg'], expr ) # delegatable will enter the next level
else:
expr = ila.ite( CSR.addr == idx, CSRRegs[csrIdxName] & ~ const(setBits(CSR.ZeroRange),XLEN) , expr )
return expr
def set_next_pc(self, index):
self.pc_wait = ((self.bar_sync_inst[index]) |
(self.bar_arrive_inst[index]) |
(self.bar_aux_inst[index])) & (
~(self.bar_sync_inst[1 - index])) & (
~(self.bar_arrive_inst[1 - index])) & (
~(self.bar_aux_inst[1 - index]))
self.model.set_next(
'pc_%d' % (index),
ila.ite(
self.pc_list[index] < (self.pc_max),
ila.ite(self.pc_wait, self.pc_list[index],
self.pc_next_list[index]), self.pc_list[index]))
def test3():
I1 = ila.Abstraction('a')
inp1 = I1.inp('inp', 1)
r1 = I1.reg('r1', 5)
I1.decode_exprs = [inp1 == 1, inp1 == 0]
uI1 = I1.add_microabstraction("mic", (r1 != 0) & (r1 < 2))
I1.set_next('r1', ila.ite(inp1 == 1, I1.const(1, 5), I1.const(0, 5)))
ur1 = uI1.reg('ur1', 5)
r1p = uI1.getreg('r1')
uI1.set_init('ur1', uI1.const(0, 5))
uI1.set_next('ur1', ur1 + 1)
uI1.set_next('r1', ila.ite(ur1 > 5, ur1, r1p))
#######################
I2 = ila.Abstraction('b')
inp2 = I2.inp('inp', 1)
r2 = I2.reg('r1', 5)
uI2 = I2.add_microabstraction("mic", (r2 != 0) & (r2 < 2))
I2.set_next('r1', ila.ite(inp2 == 1, I2.const(1, 5), I2.const(0, 5)))
I2.decode_exprs = [inp2 == 1, inp2 == 0]
ur2 = uI2.reg('ur1', 5)
r2p = uI2.getreg('r1')
uI2.set_init('ur1', uI1.const(0, 5))
uI2.set_next('ur1', ur2 + 3)
uI2.set_next('r1', ila.ite(ur2 > 5, ur2, r2p))
print 'simple signature test:'
print ila.eqcheckSimple(I1, I2)
print 'full test'
u1 = I1.newUnroller(uI1, True)
u1.addAssumption(inp1 == 1)
u1.unrollTo(20)
u1.checkAssertion(~(uI1.fetch_valid))
u1.checkAssertion(r1 == 6)
u2 = I2.newUnroller(uI2, True)
u2.addAssumption(inp2 == 1)
u2.unrollTo(20)
u2.checkAssertion(~(uI2.fetch_valid))
u2.checkAssertion(r2 == 6)
print ila.eqcheck(u1, u2, 'r1', 'r1')
def set_updates_GPR_MEM(self):
riscv = self.riscv
processor = riscv.model
processor.set_next('x0', const(0, XLEN))
for idx in range(1, 32):
#print gpr_update_list[idx]
oldexpr = processor.get_next('x%d' % idx)
nochang = self.riscv.generalRegDict['x%d' % idx]
processor.set_next(
'x%d' % idx, ila.ite(~self.take_int_or_expt, oldexpr, nochang))
oldexpr_mem = processor.get_next('mem')
processor.set_next(
'mem', ila.ite(~self.take_int_or_expt, oldexpr_mem, riscv.mem))
def aux_dest(self, opcode, src_list, index):
dest = None
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name == 'mov':
dest = src_list[0]
if opcode_name == 'and':
dest = src_list[0] & src_list[1]
if opcode_name == 'cvta':
dest = src_list[0]
if opcode_name == 'shr':
dest = ila.ashr(src_list[0], src_list[1])
if opcode_name == 'shl':
dest = src_list[0] << src_list[1]
if opcode_name == 'add':
dest = src_list[0] + src_list[1]
if opcode_name == 'sub':
dest = src_list[0] - src_list[1]
if opcode_name == 'mul':
opcode_width = opcode_split[1]
op_len = int(opcode_split[2][1:])
if opcode_width == 'wide':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest = src0 * src1
elif opcode_width == 'lo':
src0 = ila.sign_extend(src_list[0], op_len * 2)
src1 = ila.sign_extend(src_list[1], op_len * 2)
dest_long = src0 * src1
dest = dest_long[(op_len - 1):0]
if opcode_name == 'setp':
opcode_cmp = opcode_split[1]
if opcode_cmp == 'ne':
dest = ila.ite(src_list[0] != src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'gt':
dest = ila.ite(src_list[0] > src_list[1], self.pred_one,
self.pred_zero)
if opcode_cmp == 'lt':
dest = ila.ite(src_list[0] < src_list[1], self.pred_one,
self.pred_zero)
if opcode_name == 'bar':
self.bar_inst[index] = self.bar_inst[index] | (self.pc_list[0]
== self.current_pc)
if self.current_pc not in self.bar_list:
self.bar_list.append(self.current_pc)
#TODO: pc_next when bar
return dest
def readPy():
um = ila.Abstraction("aes1")
# init the state var.
# common state
state = um.reg('aes_state', 2)
opaddr = um.reg('aes_addr', 16)
oplen = um.reg('aes_len', 16)
keysel = um.reg('aes_keysel', 1)
ctr = um.reg('aes_ctr', 128)
key0 = um.reg('aes_key0', 128)
key1 = um.reg('aes_key1', 128)
xram = um.mem('XRAM', 16, 8)
aes = um.fun('aes', 128, [128, 128, 128])
# uinst state
rd_data = um.reg('rd_data', 128)
enc_data = um.reg('enc_data', 128)
byte_cnt = um.reg('byte_cnt', 16)
# state
state_next = readpyast(um, 'aes_state')
um.set_init('aes_state', um.const(1, 2))
um.set_next('aes_state', state_next)
# byte_cnt
byte_cnt_next = readpyast(um, 'byte_cnt')
um.set_next('byte_cnt', byte_cnt_next)
um.set_init('byte_cnt', um.const(0, 16))
# rd_data
rd_data_nxt = readpyast(um, 'rd_data')
um.set_next('rd_data', rd_data_nxt)
# enc_data
aes_key = ila.ite(keysel == 0, key0, key1)
aes_enc_data = ila.appfun(aes, [ctr, aes_key, rd_data])
enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data)
um.set_next('enc_data', enc_data_nxt)
# xram
uxram_nxt = readpyast(um, 'XRAM')
um.set_next('XRAM', uxram_nxt)
# the rest doesn't change.
um.set_next('aes_addr', opaddr)
um.set_next('aes_len', oplen)
um.set_ipred('aes_len', (oplen != 0) & (oplen[3:0] == 0))
um.set_next('aes_keysel', keysel)
um.set_next('aes_ctr', ctr)
um.set_next('aes_key0', key0)
um.set_next('aes_key1', key1)
return um
def auxMull_i(self, dataA, dataB):
dataAIsNeg = dataA[31]
dataBIsNeg = dataB[31]
#First calculate whether the result is positive/negative
resultIsNeg = dataAIsNeg ^ dataBIsNeg
absDataA = ila.ite(dataAIsNeg, (~dataA) + self.model.const(0b1, SCALAR_REG_BITS), dataA)
absDataB = ila.ite(dataBIsNeg, (~dataB) + self.model.const(0b1, SCALAR_REG_BITS), dataB)
#Zero-extend the data to multiply
absDataADoubleLength = ila.zero_extend(absDataA, 2 * SCALAR_REG_BITS)
absDataBDoubleLength = ila.zero_extend(absDataB, 2 * SCALAR_REG_BITS)
absResultDoubleLength = absDataADoubleLength * absDataBDoubleLength
#Adjust the pos/neg of the result
resultDoubleLength = ila.ite(resultIsNeg, (~absResultDoubleLength) + 1, absResultDoubleLength)
mulResult = resultDoubleLength[SCALAR_REG_BITS - 1:0]
return mulResult
def ptxSample(self):
instruction_map_file = 'instruction_map'
instruction_map_obj = open(instruction_map_file, 'r')
instruction_map = pickle.load(instruction_map_obj)
self.mlsreg1 = ila.sign_extend(self.sreg1,
instruction_format.LONG_REG_BITS)
self.mlsreg2 = ila.sign_extend(self.sreg2,
instruction_format.LONG_REG_BITS)
self.mldestreg = ila.sign_extend(self.sreg1 * self.sreg2,
instruction_format.LONG_REG_BITS)
return ila.ite(
self.dest == len(self.scalar_registers),
ila.ite(self.opcode == instruction_map['mul.wide'], self.mldestreg,
self.long_scalar_registers[0]),
self.long_scalar_registers[0])
def perform_instruction(self, index, program_line):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if (opcode_name != '@') and (opcode_name != 'bra'):
self.next_state_finished.append(program_line[1])
if opcode_name == 'bar':
op_len = 0
else:
op_len = int(opcode_split[-1][1:])
src_list = self.aux_generate_src_list(program_line, index, op_len)
dest = self.aux_dest(program_line[0], src_list, index)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc, dest,
self.next_state_dict[dest_str + '_%d' % (index)])
self.current_pc += 4
return
else:
if opcode_name == '@':
opcode_pred_name = program_line[1]
opcode_pred = self.model.getreg(opcode_pred_name + '_%d' %
(index))
opcode_jmp_dest = program_line[3]
opcode_jmp_target = self.pc_target[opcode_jmp_dest]
pc_jmp = ila.ite(
opcode_pred == 1,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
else:
opcode_jmp_dest = program_line[1]
opcode_jmp_target = self.pc_target[opcode_jmp_dest]
pc_jmp = ila.const(opcode_jmp_target,
instruction_format.PC_BITS)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
def synthesize():
rv = riscv()
xregs = rv.xregs
fregs = rv.fregs
pc = rv.pc
ram = rv.ram
bv = rv.model.const
rv.model.fetch_expr = rv.op
rv.model.decode_exprs = [rv.op == i for i in xrange(2)]
X1_next = ila.choice('x1', [bv(0x1, 64), xregs[0], xregs[2]])
rv.model.set_next('X1', X1_next)
rv.model.set_init('X0', bv(0x2, 64))
rv.model.set_next('X0', bv(0x2, 64))
rv.model.set_init('X2', bv(0x0, 64))
rv.model.set_next('X2', bv(0x0, 64))
rv.model.synthesize('X1', sim)
synthesized = rv.model.get_next('X1')
# expected: (if (or (eq (readmem RAM PC) 0x1) (eq (readmem RAM PC) 0x0)) X2 X1)
expected = ila.ite((ram[pc] == 1) | (ram[pc] == 0), xregs[2], xregs[1])
assert rv.model.areEqual(synthesized, expected)
def add_assumptions(self):
ptx_declaration_diff_obj = open('diff_read_only_regs', 'r')
ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj)
ptx_declaration_shared_obj = open('shared_read_only_regs', 'r')
ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj)
self.init = ila.bool(True)
for index in range(self.thread_num):
pc = self.model.getreg('pc_%d' % (index))
self.init = self.init & (pc == self.model.const(
0x0, instruction_format.PC_BITS))
i = 1
for reg_name in ptx_declaration_shared:
reg0 = self.model.getreg(reg_name + '_%d' % (0))
reg1 = self.model.getreg(reg_name + '_%d' % (1))
self.init = self.init & (reg0 == reg1)
self.init_max = self.model.const(
i, instruction_format.LONG_REG_BITS) << 59
self.init_range = self.model.const(
1, instruction_format.LONG_REG_BITS) << 58
self.init = self.init & (reg0 < self.init_max) & (
reg0 > (self.init_max - self.init_range))
i += 1
for reg in ptx_declaration_diff:
reg0 = self.model.getreg(reg + '_%d' % (0))
reg1 = self.model.getreg(reg + '_%d' % (1))
self.init = self.init & (reg0 != reg1) & (reg0 <= 128) & (
reg0 >= 0) & (reg1 <= 128) & (reg1 >= 0)
self.init = self.init & (self.en_log_register
== 0) & (self.en_check_register == 0)
bar_pred_map_obj = open('bar_pred_map', 'r')
bar_pred_map = pickle.load(bar_pred_map_obj)
bar_pred_map_obj.close()
self.check_point = ila.bool(False)
for pc in self.bar_list:
bar_pred_list = bar_pred_map[pc]
bar_pred = ila.bool(True)
for bar_pred_name in bar_pred_list:
bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (0))
bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1))
#self.condition = []
#for index in range(self.thread_num):
# self.condition.append(self.pc_list[index] >= (self.pc_max))
#self.constrain = self.condition[0]
#for index in range(1, len(self.condition)):
# self.constrain = self.constrain & self.condition[index]
self.imply = (self.check_register == self.log_register) & (
self.en_log_register == 1) & (self.en_check_register == 1)
# self.implied = self.implied & (self.mem_list[0] == self.mem_list[1])
self.predicate_bit = self.model.bit('predicate_bit')
#self.model.set_init('predicate_bit', self.model.bool(True))
self.init = self.init & (self.predicate_bit == self.model.bool(True))
self.model.set_next(
'predicate_bit',
ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def indexToVGPR(self, regNo, laneNo):
VGPR = self.vector_registers[0][0]
for regIdx in xrange(VECTOR_REGS_PER_MACHINE):
for laneIdx in xrange(VECTOR_LANES_PER_REG):
VGPR = ila.ite((regNo == regIdx) & (laneNo == laneIdx),
self.vector_registers[regIdx][laneIdx], VGPR)
return VGPR
def createmodel():
m = ila.Abstraction('alu')
m.enable_parameterized_synthesis = 1
regs = [m.reg('r%d' % i, 8) for i in xrange(4)]
opcode = m.inp('opcode', 7)
rs_index = opcode[1:0]
rt_index = opcode[3:2]
rd_index = opcode[5:4]
op = opcode[6:6]
def sel(regs, idx):
return ila.ite(
idx == 0, regs[0],
ila.ite(idx == 1, regs[1], ila.ite(idx == 2, regs[2], regs[3])))
rs = sel(regs, rs_index)
rt = sel(regs, rt_index)
res = ila.choice('op', rs + rt, rs - rt)
for i in xrange(4):
ri_next = ila.ite(rd_index == i, res, regs[i])
m.set_next('r%d' % i, ri_next)
m.fetch_expr = opcode
m.decode_exprs = [opcode == i for i in xrange(0, 128)]
m.synthesize(alusim)
for i, di in enumerate(m.decode_exprs):
for reg in xrange(4):
exp_i = m.get_next('r%d' % reg, i)
si = ila.simplify(di, exp_i)
if not m.areEqual(di, exp_i, si):
print 'decode:', di
print 'exp:', exp_i