def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
for c2 in range(c, c + 11):
# Put fixed connections in the most suitable tile
permuted_tiles = []
for tile in cfg.tiles:
if "C{}:".format(c2) in tile:
permuted_tiles.append(tile)
for tile in cfg.tiles:
if tile not in permuted_tiles:
permuted_tiles.append(tile)
cfg.tiles = permuted_tiles
nodes = ["R{}C{}_*".format(r, c2)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c2)
in x) and ("MULT9_CORE" in x or "PREADD9_CORE" in x or
"MULT18_CORE" in x or "MULT18X36_CORE" in x
or "REG18_CORE" in x)
fuzz_interconnect(config=cfg,
nodenames=nodes,
nodename_predicate=nodename_filter,
regex=True,
bidir=True,
ignore_tiles=ignore_tiles)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}')
def nn_filter(net, netnames):
""" Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally
left out by Tcl"""
return net in netnames or nets.machxo2.is_global(net) or span1_re.match(net)
def arc_filter(arc, netnames):
""" Exclude arcs whose sinks are HFSN BRANCHES (HSBX0*0{0,1}). We
will deal with them specially in another fuzzer. """
return not nets.machxo2.hfsn_branch_re.match(arc[1])
def fc_filter(arc, netnames):
""" Ignore connections between two general routing nets. These are edge buffers which vary based on location
and must be excluded from the CIB database.
"""
return not (nets.general_routing_re.match(arc[0]) and nets.general_routing_re.match(arc[1]))
interconnect.fuzz_interconnect(config=cfg, location=(5, 10),
netname_predicate=nn_filter,
arc_predicate=arc_filter,
fc_predicate=fc_filter,
netname_filter_union=True,
enable_span1_fix=True)
def main():
pytrellis.load_database("../../../database")
for job in jobs:
cfg = job["cfg"]
cfg.setup()
def nn_filter(net, netnames):
return not nets.is_cib(net)
orig_tiles = cfg.tiles
for pos in job["pos"]:
# Put fixed connections in the most appropriate tile
target_tile = None
for tile in orig_tiles:
if "R{}C{}".format(pos[0], pos[1]) in tile:
target_tile = tile
break
if target_tile is not None:
cfg.tiles = [target_tile
] + [_ for _ in orig_tiles if _ != orig_tiles]
else:
cfg.tiles = orig_tiles
interconnect.fuzz_interconnect(config=cfg,
location=pos,
netname_predicate=nn_filter,
netname_filter_union=False,
func_cib=True)
def main(args):
pytrellis.load_database("../../../database")
for job in [jobs[i] for i in args.ids]:
cfg = job["cfg"]
cfg.setup()
span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}')
def nn_filter(net, netnames):
"""I want to handle global nets that are associated with this
tile manually; any matching nets are filtered out."""
if net in job["nn_filter_extra"]:
return False
""" Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally
left out by Tcl"""
return ((net in netnames or span1_re.match(net))
and nets.is_cib(net)) or nets.machxo2.is_global(net)
def fc_filter(arc, netnames):
""" Ignore connections between two general routing nets. These are edge buffers which vary based on location
and must be excluded from the CIB database.
"""
return not (nets.general_routing_re.match(arc[0])
and nets.general_routing_re.match(arc[1]))
interconnect.fuzz_interconnect(
config=cfg,
location=job["location"],
netname_predicate=nn_filter,
fc_predicate=fc_filter,
netname_filter_union=True,
enable_span1_fix=True,
netdir_override=defaultdict(lambda: str("ignore")))
def main():
pytrellis.load_database("../../database")
cfg.setup()
span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}')
def nn_filter(net, netnames):
""" Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally
left out by Tcl"""
return ((net in netnames or span1_re.match(net))
and nets.is_cib(net)) or nets.is_global(net)
def fc_filter(arc, netnames):
""" Ignore connections between two general routing nets. These are edge buffers which vary based on location
and must be excluded from the CIB database.
"""
return not (nets.general_routing_re.match(arc[0])
and nets.general_routing_re.match(arc[1]))
interconnect.fuzz_interconnect(config=cfg,
location=(1, 16),
netname_predicate=nn_filter,
fc_predicate=fc_filter,
netname_filter_union=True,
enable_span1_fix=True)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c)
in x) and ("_GEARING_PIC_TOP_" in x or "SEIO18_CORE" in x
or "DIFFIO18_CORE" in x or "I217" in x
or "I218" in x or "SEIO33_CORE" in x
or "SIOLOGIC_CORE" in x)
def pip_filter(pip, nodes):
from_wire, to_wire = pip
return not ("ADC_CORE" in to_wire or "ECLKBANK_CORE" in to_wire
or "MID_CORE" in to_wire or "REFMUX_CORE" in to_wire
or "CONFIG_JTAG_CORE" in to_wire or "CONFIG_JTAG_CORE"
in from_wire or "REFCLOCK_MUX_CORE" in to_wire)
fuzz_interconnect(config=cfg,
nodenames=nodes,
nodename_predicate=nodename_filter,
pip_predicate=pip_filter,
regex=True,
bidir=True,
ignore_tiles=ignore_tiles)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("DLLDEL_CORE" in x or "JZ_I4" in x)
def pip_filter(x, nodes):
src, snk = x
return True
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, pip_predicate=pip_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
def per_cfg(x):
cfg = x["cfg"]
cfg.setup()
r, c = x["rc"]
cfg.sv = "../shared/empty_40.v"
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "dlldel.v"
site = "DLLDEL_CORE_R{}C{}".format(r, c)
dd = cfg.job[3:]
def get_substs(mode="DLLDEL_CORE", kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.MODE".format(dd), ["NONE", "DLLDEL_CORE"],
lambda x: get_substs(mode=x), False,
desc="DLLDEL primitive mode")
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.ENABLE".format(dd), ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("ENABLE", x)), False,
desc="DLLDEL primitive mode")
def intval(vec):
x = 0
for i, b in enumerate(vec):
if b:
x |= (1 << i)
return x
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.DEL_ADJUST".format(dd), ["PLUS", "MINUS"],
lambda x: get_substs(kv=("DEL_ADJUST", x)), False)
nonrouting.fuzz_word_setting(cfg, "DLLDEL{}.ADJUST".format(dd), 9,
lambda x: get_substs(kv=("ADJUST", str(intval(x)))))
nonrouting.fuzz_enum_setting(cfg, empty, "DLLDEL{}.CLKINMUX".format(dd), ["CLKIN", "INV"],
lambda x: get_substs(kv=("CLKIN", x), mux=True), False)
fuzzloops.parallel_foreach(configs, per_cfg)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
kws = config["keywords"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and any(kw in x for kw in kws)
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
def main():
for locs, cfg in configs:
cfg.setup()
nodes = []
for r, c in locs:
nodes += ["R{}C{}_HPBX{:02}00".format(r, c, i) for i in range(8)]
fuzz_interconnect(config=cfg,
nodenames=nodes,
regex=False,
bidir=False,
full_mux_style=True)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("DQSBUF_CORE" in x or "DQS_TOP" in x)
def pip_filter(x, nodes):
src, snk = x
return "IOLOGIC_CORE" not in snk and "DDRDLL_CORE" not in src
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, pip_predicate=pip_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
def main():
cfg.setup()
nodes = ["R37C73_JHPRX{}_CMUX_CORE_CMUX3".format(i) for i in range(16)] + \
["R37C73_JHPRX{}_CMUX_CORE_CMUX2".format(i) for i in range(16)] + \
["R37C73_JHPRX{}_CMUX_CORE_CMUX1".format(i) for i in range(16)] + \
["R37C73_JHPRX{}_CMUX_CORE_CMUX0".format(i) for i in range(16)] + \
["R37C73_JDCSMUXOUT_DCSMUX_CORE_DCSMUX{}".format(i) for i in range(4)]
fuzz_interconnect(config=cfg,
nodenames=nodes,
regex=False,
bidir=False,
full_mux_style=True)
misc_nodes = []
for i in range(4):
misc_nodes.append("R37C73_JCLKI_DCC_DCC{}".format(i))
misc_nodes.append("R37C73_JCE_DCC_DCC{}".format(i))
misc_nodes.append("R37C73_JCLKO_DCC_DCC{}".format(i))
for q in ("UL", "UR", "LL", "LR"):
for i in range(4):
misc_nodes.append(f"R37C73_JJCLK{q}_CMUX_CORE_CMUX{i}")
misc_nodes.append(f"R37C73_JJCLK{q}_DCSMUX_CORE_DCSMUX{i}")
for i in range(4):
misc_nodes.append(f"R37C73_JCLK0_DCS_DCSIP{i}")
misc_nodes.append(f"R37C73_JCLK1_DCS_DCSIP{i}")
misc_nodes.append(f"R37C73_JDCS{i}_CMUX_CORE_CMUX0")
misc_nodes.append(f"R37C73_JDCS{i}_CMUX_CORE_CMUX1")
misc_nodes.append(f"R37C73_JDCS{i}_CMUX_CORE_CMUX2")
misc_nodes.append(f"R37C73_JDCS{i}_CMUX_CORE_CMUX3")
misc_nodes.append(f"R37C73_JDCSOUT_DCS_DCSIP{i}")
misc_nodes.append(f"R37C73_JSEL_DCS_DCSIP{i}")
misc_nodes.append(f"R37C73_JSELFORCE_DCS_DCSIP{i}")
for i in range(2):
misc_nodes.append(f"R37C73_JCLKOUT_PCLKDIV_PCLKDIV{i}")
misc_nodes.append(f"R37C73_JLSRPDIV_PCLKDIV_PCLKDIV{i}")
for j in range(3):
misc_nodes.append(f"R37C73_JPCLKDIVTESTINP{j}_PCLKDIV_PCLKDIV{i}")
misc_nodes.append(f"R37C73_JCLKIN_PCLKDIV_PCLKDIV{i}")
for i in range(4):
for j in range(7):
misc_nodes.append("R37C73_JTESTINP{}_DCSMUX_CORE_DCSMUX{}".format(
j, i))
for j in range(5):
misc_nodes.append("R37C73_JTESTINP{}_CMUX_CORE_CMUX{}".format(
j, i))
misc_nodes.append("R37C73_JGSR_N_GSR_CORE_GSR_CENTER")
misc_nodes.append("R37C73_JCLK_GSR_CORE_GSR_CENTER")
fuzz_interconnect(config=cfg,
nodenames=misc_nodes,
regex=False,
bidir=False,
full_mux_style=False)
def main():
pytrellis.load_database("../../database")
for job in jobs:
loc, cfg = job
cfg.setup()
def nn_filter(net, netnames):
return "EBR" in net
interconnect.fuzz_interconnect(config=cfg, location=loc,
netname_predicate=nn_filter,
netname_filter_union=False,
func_cib=True)
def main():
pytrellis.load_database("../../database")
for job in jobs:
loc, prefix, cfg = job
cfg.setup()
def nn_filter(net, netnames):
return "PLL" in net or "CLKFB" in net or "CLKINT" in net or "REFCLK" in net
interconnect.fuzz_interconnect(config=cfg, location=loc,
netname_predicate=nn_filter,
netname_filter_union=False,
func_cib=True,
nonlocal_prefix=prefix)
def main():
pytrellis.load_database("../../../database")
cfg.setup()
span1_re = re.compile(r'R\d+C\d+_[VH]01[NESWTLBR]\d{4}')
def nn_filter(net, netnames):
""" Match nets that are: in the tile according to Tcl, global nets, or span-1 nets that are accidentally
left out by Tcl"""
return net in netnames or nets.is_global(net) or span1_re.match(net)
interconnect.fuzz_interconnect(config=cfg,
location=(19, 33),
netname_predicate=nn_filter,
netname_filter_union=True,
enable_span1_fix=True)
def per_cib(cib):
rc, cfg = cib
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
r, c = rc
# CIB F/Q "used" bits
nodes = ["R{}C{}_JF{}".format(r, c, i) for i in range(8)]
nodes += ["R{}C{}_JQ{}".format(r, c, i) for i in range(8)]
node_data = lapie.get_node_data(cfg.udb, nodes)
for n in node_data:
to_wire = n.name
setting_name = to_wire.split("_")[1] + "_USED"
from_wire = None
for p in n.uphill_pips:
if "CIBTEST" not in p.from_wire:
from_wire = p.from_wire
break
assert from_wire is not None
arcs_attr = r', \dm:arcs ="{}.{}"'.format(to_wire, from_wire)
nonrouting.fuzz_enum_setting(
cfg, empty, "CIB." + setting_name, ["NO", "YES"],
lambda x: dict(arcs_attr=arcs_attr)
if x == "YES" else {}, False)
# CIBMUXIN -> CIBMUXOUT
cfg.sv = "cib_iomux_40.v"
for x in ("A", "B", "C", "D"):
# Stop Radiant trying to tie unused outputs; as this causes weird bit patterns
extra_arcs = []
for i in range(8):
for x2 in ("A", "B", "C", "D"):
if x2 == x:
continue
extra_arcs.append(
"R{r}C{c}_JCIBMUXOUT{x}{i}.R{r}C{c}_JCIBMUXINA{i}".
format(r=r, c=c, x=x2, i=i))
cibmuxout = [
"R{}C{}_JCIBMUXOUT{}{}".format(r, c, x, i) for i in range(8)
]
fuzz_interconnect(
config=cfg,
nodenames=cibmuxout,
regex=False,
bidir=False,
full_mux_style=True,
extra_substs=dict(extra_arc=" ".join(extra_arcs)))
def main():
pytrellis.load_database("../../database")
for job in jobs:
loc, cfg = job
cfg.setup()
def nn_filter(net, netnames):
return ("MULT" in net) or ("ADD" in net) or ("JMUI" in net) or ("JP" in net) \
or ("DSP" in net) or ("JSRO" in net) or ("JNEXTR" in net) \
or ("JCFB" in net) or ("JPSR"in net) or ("JMSR" in net) or ("JR" in net) \
or ("ALU" in net) or ("JCO" in net) or ("JSOURCE" in net)
interconnect.fuzz_interconnect(config=cfg,
location=loc,
netname_predicate=nn_filter,
netname_filter_union=False,
func_cib=True)
def main(args):
pytrellis.load_database("../../../database")
for job in [jobs[i] for i in args.ids]:
cfg = job["cfg"]
cfg.setup()
if args.i:
# Fuzz basic routing, ignore fixed connections to/from I/O pads.
interconnect.fuzz_interconnect(config=cfg, location=job["pos"],
netname_predicate=job["nn_filter"],
netdir_override=defaultdict(lambda : str("ignore")),
fc_predicate=fc_filter,
netname_filter_union=False,
enable_span1_fix=True)
if args.m and job["missing_nets"]:
interconnect.fuzz_interconnect_with_netnames(config=cfg,
netnames=job["missing_nets"],
fc_predicate=fc_filter,
netname_filter_union=False,
bidir=True,
netdir_override=defaultdict(lambda : str("ignore")))
if args.p and job["bank"]:
# I/O connections in the left/right tiles exist as-if a column "0"
# or one past maximum is physically present.
if job["bank"].startswith("R"):
ab_only = job["bank"].endswith("S")
io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] + 1), job["bank"], ab_only)
elif job["bank"].startswith("L"):
ab_only = job["bank"].endswith("S")
io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1] - 1), job["bank"], ab_only)
else:
io_nets = mk_nets.io_conns((job["pos"][0], job["pos"][1]), job["bank"])
io_list = [io[0] for io in io_nets]
override_dict = {io[0]: io[1] for io in io_nets}
print(override_dict)
interconnect.fuzz_interconnect_with_netnames(config=cfg,
netnames=io_list,
fc_predicate=fc_filter,
netname_filter_union=False,
bidir=True,
netdir_override=override_dict)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("LRAM_CORE" in x)
fuzz_interconnect(config=cfg,
nodenames=nodes,
nodename_predicate=nodename_filter,
regex=True,
bidir=True,
ignore_tiles=ignore_tiles_17
if cfg.device == "LIFCL-17" else ignore_tiles)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c)
in x) and ("PLL_CORE" in x or "REFMUX_CORE" in x
or "FBMUX_CORE" in x)
fuzz_interconnect(config=cfg,
nodenames=nodes,
nodename_predicate=nodename_filter,
regex=True,
bidir=True,
ignore_tiles=ignore_tiles)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("ECLKDDR" in x or "DDRDLL_CORE" in x or "JCLKOUT_I" in x or "JPCLK_I" in x or "JECLK" in x)
def pip_filter(x, nodes):
src, snk = x
return True
fuzz_interconnect(config=cfg, nodenames=nodes, nodename_predicate=nodename_filter, pip_predicate=pip_filter, regex=True, bidir=True, ignore_tiles=ignore_tiles)
cfg.sv = "../shared/empty_40.v"
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "ddrdll.v"
site = "DDRDLL_CORE_R{}C{}".format(r, c)
def get_substs(mode="DDRDLL_CORE", kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config, site=site)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.MODE", ["NONE", "DDRDLL_CORE"],
lambda x: get_substs(mode=x), False,
desc="DDRDLL primitive mode")
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.GSR", ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("GSR", x)), False,
desc="DDRDLL GSR mask")
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.ENA_ROUNDOFF", ["ENABLED", "DISABLED"],
lambda x: get_substs(kv=("ENA_ROUNDOFF", x)), False)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.FORCE_MAX_DELAY", ["CODE_OR_LOCK_FROM_DLL_LOOP", "FORCE_LOCK_AND_CODE"],
lambda x: get_substs(kv=("FORCE_MAX_DELAY", x)), False)
nonrouting.fuzz_enum_setting(cfg, empty, "DDRDLL.RSTMUX", ["RST", "INV"],
lambda x: get_substs(kv=("RST", x), mux=True), False)
def main():
pytrellis.load_database("../../../database")
for job in jobs:
loc, prefix, cfg = job
cfg.setup()
def nn_filter(net, netnames):
return "PLL" in net or "CLKFB" in net or "CLKINT" in net or "REFCLK" in net
def arc_filter(arc, netnames):
# Skip broken PLL route-throughs
src, dest = arc
return "JREFCLK_PLL" not in src or "JQ" not in dest
interconnect.fuzz_interconnect(config=cfg,
location=loc,
netname_predicate=nn_filter,
arc_predicate=arc_filter,
netname_filter_union=False,
func_cib=True,
nonlocal_prefix=prefix)
def main():
cfg.setup()
r = 16
c = 22
nodes = ["R{}C{}_J*".format(r, c)]
extra_sources = []
extra_sources += [
"R{}C{}_H02E{:02}01".format(r, c + 1, i) for i in range(8)
]
extra_sources += [
"R{}C{}_H06E{:02}03".format(r, c + 3, i) for i in range(4)
]
extra_sources += [
"R{}C{}_V02N{:02}01".format(r - 1, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_V06N{:02}03".format(r - 3, c, i) for i in range(4)
]
extra_sources += [
"R{}C{}_V02S{:02}01".format(r + 1, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_V06S{:02}03".format(r + 3, c, i) for i in range(4)
]
extra_sources += [
"R{}C{}_H02W{:02}01".format(r, c - 1, i) for i in range(8)
]
extra_sources += [
"R{}C{}_H06W{:02}03".format(r, c - 3, i) for i in range(4)
]
fuzz_interconnect(config=cfg,
nodenames=nodes,
regex=True,
bidir=True,
ignore_tiles=set(["TAP_PLC_R16C14:TAP_PLC"]))
fuzz_interconnect(config=cfg,
nodenames=extra_sources,
regex=False,
bidir=False,
ignore_tiles=set(["TAP_PLC_R16C14:TAP_PLC"]))
def main():
for feed, rc, ndcc, side, cfg in configs:
cfg.setup()
r, c = rc
nodes = []
mux_nodes = []
for i in range(ndcc):
for j in range(2):
nodes.append("R{}C{}_J{}{}_CMUX_CORE_CMUX{}".format(cr, cc, feed, i, j))
nodes.append("R{}C{}_J{}{}_CMUX_CORE_CMUX{}".format(cr, cc, feed, i, j))
nodes.append("R{}C{}_J{}{}_DCSMUX_CORE_DCSMUX{}".format(cr, cc, feed, i, j))
nodes.append("R{}C{}_J{}{}_DCSMUX_CORE_DCSMUX{}".format(cr, cc, feed, i, j))
nodes.append("R{}C{}_JCLKO_DCC_DCC{}".format(r, c, i))
nodes.append("R{}C{}_JCE_DCC_DCC{}".format(r, c, i))
nodes.append("R{}C{}_JCLKI_DCC_DCC{}".format(r, c, i))
mux_nodes.append("R{}C{}_J{}{}_{}MID_CORE_{}MIDMUX".format(r, c, feed, i, side, side))
for i in range(4):
nodes.append("R{}C{}_JTESTINP{}_{}MID_CORE_{}MIDMUX".format(r, c, i, side, side))
fuzz_interconnect(config=cfg, nodenames=nodes, regex=False, bidir=False, full_mux_style=False)
fuzz_interconnect(config=cfg, nodenames=mux_nodes, regex=False, bidir=False, full_mux_style=True)
def pip_filter(pip, nodes):
from_wire, to_wire = pip
return "PCLKT" in to_wire or "PCLKCIB" in to_wire
fuzz_interconnect(config=cfg, nodenames=["R{}C{}_J*".format(r, c)], regex=True, bidir=False, full_mux_style=False,
pip_predicate=pip_filter)
def main():
for config in configs:
cfg = config["cfg"]
cfg.setup()
r, c = config["rc"]
nodes = ["R{}C{}_*".format(r, c)]
def nodename_filter(x, nodes):
return ("R{}C{}_".format(r, c) in x) and ("ECLK" in x)
def pip_filter(x, nodes):
src, snk = x
return "PLL_CORE" not in src and "FBMUX_CORE" not in src and "FBMUX_CORE" not in snk \
and "I217" not in snk and "I218" not in snk and "ECLKDDR" not in src \
and "DQS_TOP" not in snk and "PADDI" not in src and "INCK_IOLOGIC" not in src
fuzz_interconnect(config=cfg,
nodenames=nodes,
nodename_predicate=nodename_filter,
pip_predicate=pip_filter,
regex=True,
bidir=True,
ignore_tiles=ignore_tiles)
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "osc.v"
def bin_to_int(x):
val = 0
mul = 1
for bit in x:
if bit:
val |= mul
mul *= 2
return val
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode, cmt="//" if mode == "NONE" else "", config=config)
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.MODE", ["NONE", "OSC_CORE"],
lambda x: get_substs(mode=x), False,
desc="OSC_CORE primitive mode")
nonrouting.fuzz_word_setting(cfg, "OSC_CORE.HF_CLK_DIV", 8,
lambda x: get_substs(mode="OSC_CORE", kv=("HF_CLK_DIV", str(bin_to_int(x)))),
desc="high frequency oscillator output divider")
nonrouting.fuzz_word_setting(cfg, "OSC_CORE.HF_SED_SEC_DIV", 8,
lambda x: get_substs(mode="OSC_CORE", kv=("HF_SED_SEC_DIV", str(bin_to_int(x)))),
desc="high frequency oscillator output divider")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.DTR_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("DTR_EN", x)), False,
desc="")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.HF_FABRIC_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("HF_FABRIC_EN", x)), False,
desc="enable HF oscillator trimming from input pins")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.HF_OSC_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("HF_OSC_EN", x)), False,
desc="enable HF oscillator")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.HFDIV_FABRIC_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("HFDIV_FABRIC_EN", x)), False,
desc="enable HF divider from parameter")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.LF_FABRIC_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("LF_FABRIC_EN", x)), False,
desc="enable LF oscillator trimming from input pins")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.LF_OUTPUT_EN", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("LF_OUTPUT_EN", x)), False,
desc="enable LF oscillator output")
nonrouting.fuzz_enum_setting(cfg, empty, "OSC_CORE.DEBUG_N", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="OSC_CORE", kv=("DEBUG_N", x)), False,
desc="enable debug mode")
# Fuzz oscillator routing
cfg.sv = "../shared/route_40.v"
nodes = ["R1C77_JLFCLKOUT_OSC_CORE", "R1C77_JHFCLKOUT_OSC_CORE",
"R1C77_JHFSDCOUT_OSC_CORE", "R1C77_JHFCLKCFG_OSC_CORE",
"R1C77_JHFOUTEN_OSC_CORE", "R1C77_JHFSDSCEN_OSC_CORE"]
for i in range(9):
nodes.append("R1C77_JHFTRMFAB{}_OSC_CORE".format(i))
nodes.append("R1C77_JLFTRMFAB{}_OSC_CORE".format(i))
fuzz_interconnect(config=cfg, nodenames=nodes, regex=False, bidir=True, full_mux_style=False)
def main():
cfg.setup()
empty = cfg.build_design(cfg.sv, {})
cfg.sv = "gsr.v"
def bin_to_int(x):
val = 0
mul = 1
for bit in x:
if bit:
val |= mul
mul *= 2
return val
def get_substs(mode="NONE", default_cfg=False, kv=None, mux=False):
if kv is None:
config = ""
elif mux:
val = "#SIG"
if kv[1] in ("0", "1"):
val = kv[1]
if kv[1] == "INV":
val = "#INV"
config = "{}::::{}={}".format(mode, kv[0], val)
else:
config = "{}:::{}={}".format(mode, kv[0], kv[1])
return dict(mode=mode,
cmt="//" if mode == "NONE" else "",
config=config)
nonrouting.fuzz_enum_setting(cfg,
empty,
"GSR_CORE.MODE", ["NONE", "GSR_CORE"],
lambda x: get_substs(mode=x),
False,
desc="GSR_CORE primitive mode")
nonrouting.fuzz_enum_setting(
cfg,
empty,
"GSR_CORE.GSR", ["ENABLED", "DISABLED"],
lambda x: get_substs(mode="GSR_CORE", kv=("GSR", x)),
False,
desc="enable global set/reset")
nonrouting.fuzz_enum_setting(
cfg,
empty,
"GSR_CORE.GSR_SYNC", ["ASYNC", "SYNC"],
lambda x: get_substs(mode="GSR_CORE", kv=("GSR_SYNC", x)),
False,
desc="synchronise global set/reset")
nonrouting.fuzz_enum_setting(
cfg,
empty,
"GSR_CORE.CLKMUX", ["CLK", "INV"],
lambda x: get_substs(mode="GSR_CORE", kv=("CLK", x), mux=True),
False,
desc="")
nonrouting.fuzz_enum_setting(
cfg,
empty,
"GSR_CORE.GSR_NMUX", ["GSR_N", "INV"],
lambda x: get_substs(mode="GSR_CORE", kv=("GSR_N", x), mux=True),
False,
desc="")
# Fuzz GSR routing
cfg.sv = "../shared/route_40.v"
nodes = [
"R28C49_JGSR_N_GSR_CORE_GSR_CENTER", "R28C49_JCLK_GSR_CORE_GSR_CENTER",
"R28C49_JGSROUT_GSR_CORE_GSR_CENTER"
]
fuzz_interconnect(config=cfg,
nodenames=nodes,
regex=False,
bidir=True,
full_mux_style=False)
def main():
for rc, cfg, ignore in configs:
cfg.setup()
r, c = rc
nodes = ["R{}C{}_J*".format(r, c)]
extra_sources = []
extra_sources += [
"R{}C{}_H02E{:02}01".format(r, c + 1, i) for i in range(8)
]
extra_sources += [
"R{}C{}_H06E{:02}03".format(r, c + 3, i) for i in range(4)
]
if r != 1:
extra_sources += [
"R{}C{}_V02N{:02}01".format(r - 1, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_V06N{:02}03".format(r - 3, c, i) for i in range(4)
]
else:
extra_sources += [
"R{}C{}_V02N{:02}00".format(r, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_V06N{:02}00".format(r, c, i) for i in range(4)
]
extra_sources += [
"R{}C{}_V02S{:02}01".format(r + 1, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_V06S{:02}03".format(r + 3, c, i) for i in range(4)
]
if c != 1:
extra_sources += [
"R{}C{}_H02W{:02}01".format(r, c - 1, i) for i in range(8)
]
extra_sources += [
"R{}C{}_H06W{:02}03".format(r, c - 3, i) for i in range(4)
]
else:
extra_sources += [
"R{}C{}_H02W{:02}00".format(r, c, i) for i in range(8)
]
extra_sources += [
"R{}C{}_H06W{:02}00".format(r, c, i) for i in range(4)
]
def pip_filter(pip, nodes):
from_wire, to_wire = pip
return not ("_CORE" in from_wire or "_CORE" in to_wire
or "JCIBMUXOUT" in to_wire)
def fc_filter(to_wire):
return "CIBMUX" in to_wire or "CIBTEST" in to_wire or to_wire.startswith(
"R{}C{}_J".format(r, c))
fuzz_interconnect(config=cfg,
nodenames=nodes,
regex=True,
bidir=True,
ignore_tiles=ignore,
pip_predicate=pip_filter,
fc_filter=fc_filter)
fuzz_interconnect(config=cfg,
nodenames=extra_sources,
regex=False,
bidir=False,
ignore_tiles=ignore,
pip_predicate=pip_filter,
fc_filter=fc_filter)
