def _parse_component(self, component_file):
component_dir = os.path.dirname(component_file)
component = Component()
component.load(os.path.join(self.files_root, component_file))
if not self.main.description:
self.main.description = component.description
_file_sets = []
for file_set in component.fileSets.fileSet:
_name = file_set.name
for f in file_set.file:
f.name = os.path.normpath(os.path.join(component_dir, f.name))
self.export_files.append(f.name)
# FIXME: Harmonize underscore vs camelcase
f.file_type = f.fileType
if f.isIncludeFile == "true":
f.is_include_file = True
else:
f.is_include_file = False
f.logical_name = f.logicalName
f.copyto = ""
# FIXME: Handle duplicates. Resolution function? (merge/replace, prio ipxact/core)
_taken = False
for fs in self.file_sets:
if fs.name == file_set.name:
_taken = True
if not _taken:
_file_sets.append(
FileSet(
name=file_set.name,
file=file_set.file[:],
usage=["sim", "synth"],
))
self.file_sets += _file_sets
def _parse_component(self, component_file):
component_dir = os.path.dirname(component_file)
component = Component()
component.load(os.path.join(self.files_root, component_file))
if not self.main.description:
self.main.description = component.description
_file_sets = []
for file_set in component.fileSets.fileSet:
_name = file_set.name
for f in file_set.file:
f.name = os.path.normpath(os.path.join(component_dir, f.name))
self.export_files.append(f.name)
#FIXME: Harmonize underscore vs camelcase
f.file_type = f.fileType
if f.isIncludeFile == 'true':
f.is_include_file = True
else:
f.is_include_file = False
f.logical_name = f.logicalName
f.copyto = ""
#FIXME: Handle duplicates. Resolution function? (merge/replace, prio ipxact/core)
_taken = False
for fs in self.file_sets:
if fs.name == file_set.name:
_taken = True
if not _taken:
_file_sets.append(FileSet(name = file_set.name,
file = file_set.file[:],
usage = ['sim', 'synth']))
self.file_sets += _file_sets
def _parse_component(self, component_file):
component = Component()
component.load(component_file)
if not self.main.description:
self.main.description = component.description
_file_sets = []
for file_set in component.fileSets.fileSet:
_name = file_set.name
for f in file_set.file:
self.export_files.append(f.name)
#FIXME: Harmonize underscore vs camelcase
f.file_type = f.fileType
if f.isIncludeFile == 'true':
f.is_include_file = True
else:
f.is_include_file = False
f.logical_name = f.logicalName
#FIXME: Handle duplicates. Resolution function? (merge/replace, prio ipxact/core)
_taken = False
for fs in self.file_sets:
if fs.name == file_set.name:
_taken = True
if not _taken:
_file_sets.append(
FileSet(name=file_set.name,
file=file_set.file[:],
usage=['sim', 'synth']))
self.file_sets += _file_sets
def write_c_header(f, offset, name):
component = Component()
component.load(f)
if component.memoryMaps:
return print_c_header(component.memoryMaps, offset, name)
else:
return "No memory maps found"
bname = mname
for reg in sorted(block.register, key=lambda a: a.addressOffset):
reg_name = '{}_{}'.format(bname,
reg.name.upper().replace('-', '_'))
reg_addr = '0x{:08X}'.format(offset + block.baseAddress +
reg.addressOffset)
if reg.size in [8, 16, 32, 64]:
reg_access = 'RO_' if reg.access == 'read-only' else ''
of.write('#define {} IPYXACT_{}REG_{}({})\n'.format(
reg_name, reg_access, reg.size, reg_addr))
else:
of.write("#define {} {}\n".format(reg_name, reg_addr))
if reg.field:
write_reg_fields(reg, reg_name)
if __name__ == '__main__':
args = parse_args()
with open(args.ipxact_file) as f:
name = None
offset = 0
component = Component()
component.load(f)
with open_output(args.output_file) as of:
write_prologue(of, args)
write_memory_maps(of, component.memoryMaps, offset, name)
write_epilogue(of, args)
for portMap in busInterface.portMaps.portMap:
if portMap.logicalPort.vector:
log_range = '[{}:{}]'.format(portMap.logicalPort.vector.left,
portMap.logicalPort.vector.right)
else:
log_range = ''
if portMap.physicalPort.vector:
phy_range = '[{}:{}]'.format(portMap.physicalPort.vector.left,
portMap.physicalPort.vector.right)
else:
phy_range = ''
print("{}{} => {}{}".format(portMap.logicalPort.name,
log_range,
portMap.physicalPort.name,
phy_range))
return ifs
if __name__ == "__main__":
f = open(sys.argv[1])
component = Component()
component.load(f)
if component.busInterfaces is not None:
ifs = get_businterfaces(component.busInterfaces)
print(ifs)
else:
print("No bus interfaces found in file")
f.close()
def write_c_header(f, offset, name):
component = Component()
component.load(f)
return print_c_header(component.memoryMaps, offset, name)
clk = str(cfg['General']['Clock'])
rst = str(cfg['General']['Reset'])
rst_level = int(cfg['General']['ResetActiveLevel'])
rst_is_sync = int(cfg['General']['ResetIsSync'])
lang = str(cfg['Doc']['Language'])
#### i18n ####
t = gettext.translation('ipxact', 'languages', languages=[lang], fallback=True)
_ = t.ugettext
component = Component()
component.load(args.xml_path[0].name)
addressBlock = component.memoryMaps.memoryMap[0].addressBlock[0]
busByteWidth = component.memoryMaps.memoryMap[0].addressBlock[0].width / 8
busBitWidth = component.memoryMaps.memoryMap[0].addressBlock[0].width
addr_width = component.memoryMaps.memoryMap[0].addressBlock[0].width
data_width = component.memoryMaps.memoryMap[0].addressBlock[0].register[0].size
fileName = component.name.lower() + '_table_regs_ov.adoc'
lookup = TemplateLookup(directories=['templates'],
input_encoding='utf-8',
output_encoding='utf-8',
def write_markdown(f, offset, name):
component = Component()
component.load(f)
return print_memorymaps(component.memoryMaps, offset, name)
def write_markdown(f, offset, name):
component = Component()
component.load(f)
return print_memorymaps(component.memoryMaps, offset, name)
def write_filesets(f):
component = Component()
component.load(f)
return print_filesets(component.fileSets)
def write_c_header(f, offset, name):
component = Component()
component.load(f)
return print_c_header(component.memoryMaps, offset, name)
