def bench_backend_conversion():
"""This bench is used to test the functionality"""
# instantiate module and clock
inst = backend(clock, reset, start_block, data_in, write_addr,
valid_data, data_out, ready, addr, num_enc_bytes)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
"""testbench for conversion purpose"""
yield clock.posedge
print("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def bench_backend_conversion():
"""This bench is used to test the functionality"""
# instantiate module and clock
inst = backend(clock, reset, start_block, data_in,
write_addr, valid_data, data_out,
ready, addr, num_enc_bytes)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
"""testbench for conversion purpose"""
yield clock.posedge
print("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def bench_backend():
"""This bench is used to test the functionality"""
# instantiate module and clock
inst = backend(clock, reset, start_block, data_in, write_addr,
valid_data, data_out, ready, addr, num_enc_bytes)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0] * 64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print("===================")
for i in range(addr):
print("outputs_hdl %d" % output_model[i])
print("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print("outputs_soft %d" % int(output_ref[i], 2))
print("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
return tbstim, inst, inst_clock
def bench_backend():
"""This bench is used to test the functionality"""
# instantiate module and clock
inst = backend(clock, reset, start_block, data_in,
write_addr, valid_data, data_out,
ready, addr, num_enc_bytes)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""stimulus generates inputs for entropy coder"""
# reset the module
output_model = [0]*64
yield pulse_reset(reset, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
write_addr.next = 64
for i in range(64):
data_in.next = i % 25
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
for _ in range(35):
yield clock.posedge
# start the blocks
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 16
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 47
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Y data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 28
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cb data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 40
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
yield toggle_signal(start_block, clock)
# write Cr data into input buffer
valid_data.next = True
yield clock.posedge
for i in range(64):
data_in.next = i % 31
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
write_addr.next = write_addr + 1
valid_data.next = False
yield clock.posedge
while not ready:
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
yield toggle_signal(start_block, clock)
while not ready:
index = int(addr)
output_model[index] = int(data_out)
yield clock.posedge
print ("===================")
for i in range(addr):
print ("outputs_hdl %d" % output_model[i])
print ("======================")
# get outputs from reference values
output_ref = []
output_ref = backend_soft()
for i in range(len(output_ref)):
print ("outputs_soft %d" % int(output_ref[i], 2))
print ("===========================")
# compare reference and HDL outputs
for i in range(len(output_ref)):
assert int(output_ref[i], 2) == output_model[i]
raise StopSimulation
return tbstim, inst, inst_clock
