def bench_divider(): """The module where we pass tests into divider block""" # instantiation of clock and divider inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) @instance def tbstim(): """Test cases are given here""" # reset signal yield pulse_reset(reset, clock) list_output = [] list_output_ref = [] # all the possible tests from -2048 to 2048 given here for dividend_temp in range(-2**(width_data), 2**(width_data), 1): for divisor_temp in range(0, 256, 1): dividend.next = dividend_temp divisor.next = divisor_temp result = divider_ref(dividend_temp, divisor_temp) list_output_ref.append(result) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) # pop the zeroes stored in the list because of pipelining list_output.pop(0) list_output.pop(0) list_output.pop(0) list_output.pop(0) # compare reference design divider output with that of HDL divider for item1, item2 in zip(list_output, list_output_ref): print("quotient %d quotient_ref %d" % (item1, item2)) assert item1 == item2 raise StopSimulation return tbstim, inst, inst_clock
def bench_divider(): """The module where we pass tests into divider block""" # instantiation of clock and divider inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) @instance def tbstim(): """Test cases are given here""" # reset signal yield pulse_reset(reset, clock) list_output = [] list_output_ref = [] # all the possible tests from -2048 to 2048 given here for dividend_temp in range(-2**(width_data), 2**(width_data), 1): for divisor_temp in range(0, 256, 1): dividend.next = dividend_temp divisor.next = divisor_temp result = divider_ref(dividend_temp, divisor_temp) list_output_ref.append(result) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) yield clock.posedge list_output.append(int(quotient)) # pop the zeroes stored in the list because of pipelining list_output.pop(0) list_output.pop(0) list_output.pop(0) list_output.pop(0) # compare reference design divider output with that of HDL divider for item1, item2 in zip(list_output, list_output_ref): print ("quotient %d quotient_ref %d" % (item1, item2)) assert item1 == item2 raise StopSimulation return tbstim, inst, inst_clock
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset
def bench_divider(): """Wrapper used for conversion purpose""" # instantiatiom of divider, clock and reset inst = divider(clock, reset, dividend, divisor, quotient) inst_clock = clock_driver(clock) inst_reset = reset_on_start(reset, clock) @instance def tbstim(): """Dummy tests to convert the module""" yield clock.posedge print ("Conversion done!!") raise StopSimulation return tbstim, inst, inst_clock, inst_reset