config_data_width=32,
config_addr_width=8,
cycle_count_width=16,
add_clk_enable=True,
add_flush=True)
# print(f"Supports Stencil Valid: {lake_dut.supports('stencil_valid')}")
# if do_config_lift, then do not need_config_lift later
return pond_dut, not do_config_lift, use_sram_stub, tsmc_info
if __name__ == "__main__":
pond_dut = Pond(
data_width=16, # CGRA Params
mem_depth=32,
default_iterator_support=2,
interconnect_input_ports=2, # Connection to int
interconnect_output_ports=2,
mem_input_ports=1,
mem_output_ports=1,
cycle_count_width=16,
add_clk_enable=True,
add_flush=True)
# Lift config regs and generate annotation
# lift_config_reg(pond_dut.internal_generator)
extract_formal_annotation(pond_dut, "pond.txt")
verilog(pond_dut, filename="pond.sv", optimize_if=False)
self._agg[idx][0][self._agg_write_addr[idx][clog2(self.fetch_width) - 1, 0]]\
= self._data_in[idx]
else:
self._agg[idx][self._agg_write_addr[idx]
[self._agg_write_addr[0].width - 1, clog2(self.fetch_width)]]\
[self._agg_write_addr[idx][clog2(self.fetch_width) - 1, 0]]\
= self._data_in[idx]
@always_comb
def agg_to_sram(self):
for i in range(self.fetch_width):
self._data_out[i] = \
self._agg[self._input_port_sel_addr][self._agg_read_addr[self._input_port_sel_addr]][i]
@always_ff((posedge, "clk"), (negedge, "rst_n"))
def increment_cycle_count(self):
if ~self._rst_n:
self._cycle_count = 0
else:
self._cycle_count = self._cycle_count + 1
if __name__ == "__main__":
lake_dut = AggFormal()
lift_config_reg(lake_dut.internal_generator)
extract_formal_annotation(lake_dut, "agg_formal_annotation.txt")
verilog(lake_dut, filename="agg_formal.sv",
optimize_if=False)
self.add_code(self.tb_ctrl)
for idx in range(self.interconnect_output_ports):
self.add_code(self.tb_to_out, idx=idx)
@always_ff((posedge, "clk"))
def tb_ctrl(self):
if self._read:
self._tb[self._output_port_sel_addr][self._tb_write_addr[self._output_port_sel_addr][1, 0]] = \
self._data_in
@always_comb
def tb_to_out(self, idx):
self._data_out[idx] = self._tb[idx][self._tb_read_addr[idx][3, 2]][
self._tb_read_addr[idx][1, 0]]
@always_ff((posedge, "clk"), (negedge, "rst_n"))
def increment_cycle_count(self):
if ~self._rst_n:
self._cycle_count = 0
else:
self._cycle_count = self._cycle_count + 1
if __name__ == "__main__":
tb_dut = TBFormal()
lift_config_reg(tb_dut.internal_generator)
extract_formal_annotation(tb_dut, 'tb_formal_annotation.txt')
verilog(tb_dut, filename="tb_formal.sv", optimize_if=False)
def set_sram_addr(self):
if self._write:
self._addr = self._write_addr[clog2(self.mem_depth) - 1, 0]
else:
self._addr = self._read_addr[clog2(self.mem_depth) - 1, 0]
@always_ff((posedge, "clk"), (negedge, "rst_n"))
def increment_cycle_count(self):
if ~self._rst_n:
self._cycle_count = 0
else:
self._cycle_count = self._cycle_count + 1
@always_ff((posedge, "clk"), (negedge, "rst_n"))
def set_valid_out(self):
if ~self._rst_n:
self._valid_out = 0
else:
self._valid_out = self._cen_to_sram & ~self._wen_to_sram
if __name__ == "__main__":
lake_dut = SRAMFormal()
# Lift config regs and generate annotation
lift_config_reg(lake_dut.internal_generator)
extract_formal_annotation(lake_dut, "sram_formal_annotation.txt")
verilog(lake_dut, filename="sram_formal.sv", optimize_if=False)
# additional_passes={"lift config regs": lift_config_reg})