def test_V1(self):
"""Lcapy: test V1"""
a = Circuit()
a.add('V1 1 0 10')
self.assertEqual(a.V1.V.dc, 10, "Incorrect voltage")
def test_V1(self):
"""Lcapy: test V1"""
a = Circuit()
a.add('V1 1 0 10')
self.assertEqual(a.V1.V.dc, 10, "Incorrect voltage")
def test_VRC1(self):
"""Lcapy: check VRC circuit
"""
a = Circuit()
a.add('V1 1 0 {V1 / s}')
a.add('R1 1 2')
a.add('C1 2 0')
# Note, V1 acts as a short-circuit for the impedance/admittance
self.assertEqual2(
a.Z(1, 2), (R('R1') | C('C1')).Z, "Z incorrect across R1")
self.assertEqual2(
a.Z(2, 0), (R('R1') | C('C1')).Z, "Z incorrect across C1")
self.assertEqual2(a.Z(1, 0), R(0).Z, "Z incorrect across V1")
self.assertEqual2(
a.Y(1, 2), (R('R1') | C('C1')).Y, "Y incorrect across R1")
self.assertEqual2(
a.Y(2, 0), (R('R1') | C('C1')).Y, "Y incorrect across C1")
# This has a non-invertible A matrix.
# self.assertEqual2(a.Y(1, 0), R(0).Y, "Y incorrect across V1")
self.assertEqual2(a.Voc(1, 0).s, V('V1 / s').Voc.s, "Voc incorrect across V1")
self.assertEqual(a.is_ivp, False, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
def test_filtered_noise1(self):
"""Lcapy: check circuit filtered noise"""
a = Circuit()
a.add('V1 1 0 noise 3')
a.add('R1 1 2 2')
a.add('C1 2 0 4')
def test_RC1(self):
"""Lcapy: check RC network
"""
a = Circuit()
a.add('R1 1 2')
a.add('C1 2 0')
self.assertEqual2(a.impedance(1, 2),
R('R1').impedance, "Z incorrect for R1.")
self.assertEqual2(a.impedance(2, 0),
C('C1').impedance, "Z incorrect for C1.")
self.assertEqual2(a.impedance(1, 0), (R('R1') + C('C1')).impedance,
"Z incorrect for R1 + C1.")
self.assertEqual2(a.admittance(1, 2), R('R1').Y, "Y incorrect for R1.")
self.assertEqual2(a.admittance(2, 0), C('C1').Y, "Y incorrect for C1.")
self.assertEqual2(a.admittance(1, 0), (R('R1') + C('C1')).Y,
"Y incorrect for R1 + C1.")
self.assertEqual2(a.Isc(1, 0), I(0).Isc, "Isc incorrect")
self.assertEqual(a.R1.Z, expr('R1'), "Z incorrect")
self.assertEqual(a.R1.R, expr('R1'), "R incorrect")
self.assertEqual(a.R1.X, 0, "X incorrect")
self.assertEqual(a.C1.Y, expr('j * omega * C1'), "Y incorrect")
self.assertEqual(a.C1.G, 0, "G incorrect")
self.assertEqual(a.C1.B, expr('-omega * C1'), "B incorrect")
def test_TF(self):
a = Circuit("""
TF 2 0 1 0 k
R 2 0""")
self.assertEqual(a.impedance(1, 0), expr('R / k**2'),
"incorrect impedance")
def test_sub(self):
a = Circuit("""
V1 1 0 {u(t)}
R1 1 2
L1 2 0""")
self.assertEqual(a.ac().R1.V, 0, "AC model incorrect")
self.assertEqual(a.dc().R1.V, 0, "DC model incorrect")
def test_noise2(self):
"""Lcapy: check circuit noise for pair of sources"""
a = Circuit()
a.add('V1 1 0 noise 3')
a.add('V2 2 1 noise 4')
a.add('R1 2 0 5')
V1 = a.R1.V.n
self.assertEqual2(V1, Vn(5, nid=V1.nid), "Incorrect noise sum")
def test_filtered_noise2(self):
"""Lcapy: check circuit filtered noise"""
a = Circuit()
a.add('V1 1 0 noise {sqrt(4 * k * T * R)}')
a.add('R1 1 2 R')
a.add('C1 2 0 C')
self.assertEqual2(a.C1.V.n.rms(), Vt('sqrt(k * T / C)'),
"Incorrect capacitor voltage")
def test_filtered_noise3(self):
"""Lcapy: check circuit filtered noise"""
a = Circuit()
a.add('V1 1 0 noise 20')
a.add('R1 1 2 1')
a.add('C1 2 0 2')
self.assertEqual(a.C1.V.n.rms(), 5 * sqrt(2),
"Incorrect capacitor voltage")
def test_noise1(self):
"""Lcapy: check circuit noise for voltage divider"""
a = Circuit()
a.add('V1 1 0 noise 3')
a.add('R1 1 2 2')
a.add('R2 2 0 4')
V1 = a.R1.V.n
self.assertEqual2(V1, Vn(1, nid=V1.nid), "Incorrect ratio")
def test_noisy1(self):
a = Circuit()
a.add('R1 1 0')
a.add('R2 1 0')
an = a.noisy()
b = Circuit()
b.add('R1 1 0 {R1 * R2 / (R1 + R2)}')
bn = b.noisy()
self.assertEqual(an[1].V.n.expr, bn[1].V.n.expr, "Incorrect noise")
def test_causal1(self):
a = Circuit()
a.add('V1 1 0 {4 + 2 * u(t)}; down')
a.add('R1 1 2 2; right=2')
a.add('L1 2 3 2; down')
a.add('W 0 3; right')
self.assertEqual(a.sub['s'].is_causal, True, "Causal incorrect")
self.assertEqual2(a.L1.v, 2 * exp(-t) * u(t), "L current incorrect")
def test_IR1(self):
"""Lcapy: check IR circuit
"""
a = Circuit()
a.add('I1 1 0 2')
a.add('R1 1 0 1')
self.assertEqual2(a.R1.V, V(2).Voc, "Incorrect voltage")
self.assertEqual2(a[1].V, V(2).Voc, "Incorrect node voltage")
def test_IR1(self):
"""Lcapy: check IR circuit
"""
a = Circuit()
a.add('I1 1 0 2')
a.add('R1 1 0 1')
self.assertEqual2(a.R1.V, V(2).Voc, "Incorrect voltage")
self.assertEqual2(a[1].V, V(2).Voc, "Incorrect node voltage")
def test_CCVS2(self):
"""Lcapy: check CCVS
"""
a = Circuit()
a.add('H1 1 0 H1 -4')
t = a.thevenin(1, 0)
self.assertEqual(t.V, 0, "Incorrect Thevenin voltage")
self.assertEqual(t.Z, -4, "Incorrect Thevenin impedance")
self.assertEqual(a.H1.Voc, 0, "Incorrect cpt voltage")
self.assertEqual(a.H1.Z, 0, "Incorrect cpt impedance")
def test_CCVS1(self):
"""Lcapy: check CCVS
"""
a = Circuit()
a.add('V1 1 0 10')
a.add('R1 1 2 2')
a.add('V2 2 0 0')
a.add('H1 3 0 V2 2')
a.add('R2 3 0 1')
self.assertEqual2(a.R2.V, V(10).Voc, "Incorrect voltage")
def test_VRL1_dc(self):
"""Lcapy: check VRL circuit at dc
"""
a = Circuit()
a.add('V1 1 0 dc')
a.add('R1 1 2')
a.add('L1 2 0')
self.assertEqual(a.is_ivp, False, "Initial value problem incorrect")
self.assertEqual(a.is_dc, True, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
def half_bridge_topology_image():
cct = Circuit()
# the input (switches-capacitors-transformer)
cct.add('''
P1 p1a p1b; down,v=V_{in}
C1 c1a c1b; down=3
C2 c1b c2b; down=3
R1 r1a r1b; down=3,l=Rb
R2 r1b r2b; down=3,l=Rb
W r1b c1b; right
W p1a r1a; right
W p1b r2b; right
W r1a c1a; right
W r2b c2b; right
W c1a 1d; right=2
M1 1d 1g 1s nmos; right
W 1s 2d1; down
W 2d1 2d; down
M2 2d 2g 2s nmos; right
W c2b 2s; right=2
TF1 t1 t2 t3 t4 tapcore _t5 _t6; right, size=1.5
W 2d1 t3; right
Cb c1b t4; right=2
''')
# First body diode
cct.add('''
W 1d dm1b; right=0.5
W 1s dm1a; right=0.5
DM1 dm1a dm1b; up
''')
# Second body diode
cct.add('''
W 2d dm2b; right=0.5
W 2s dm2a; right=0.5
DM2 dm2a dm2b; up
''')
# The output (transformer-rectifier-inductor-capacitor)
cct.add('''
W _t6 t6; right=2
W t6 go1; down
W go1 go2; right
D1 t1 d1b; right
D2 t2 d2b; right
W d2b d1b; up
Lo d1b coa; right
Co coa go2; down
P2 p2a p2b; down, v=V_{out}
W coa p2a; right
W go2 p2b; right
''')
return cct
def push_pull_coupled_lossless_clamp_image():
cct = Circuit()
cct.add('''
P1 p1a p1b; down=10,v=V_{in}
W p1a c1a; right
W p1b c1b; right
C1 c1a c1b; down
W c1a clampret1; right=1
W clampret1 clampret2; right=4
W clampret2 t1c1; right=3
W t1c1 t1c2; down=2
W t1c2 t1c3; right
LW1 l1a t1c3; down
LW2 t1c3 l2b; down
W l1a lleak21; left=2
W lleak21 lleak2a; down=3
Lleak2 lleak2a lleak2b; down,color=red
CS2 lleak2b cs2b; left=2,color=blue,v=$V_{CS}$
W cs2b ds2a; up=2,color=blue
DS2 ds2a ds2b; up=2.5,color=blue
W ds2b clampret2; up,color=blue
W ds2a lw3a1; right=3,color=blue
W lw3a1 lw3a2; down=1,color=blue
LW3 lw3a2 lw3b; down,color=blue
LW4 lw3b lw4b; down,color=blue,fixed
W l2b lleak1a1; left=6
W lleak1a1 lleak1a; down=1.5
Lleak1 lleak1a lleak1b; down,color=red
CS1 lleak1b cs1b; left=2,color=blue,v=$V_{CS}$
W cs1b ds1a; up=2,color=blue
DS1 ds1a ds1b; up=2.5,color=blue
W ds1b clampret1; up,color=blue
W lleak1b m1d; down=0.5
W lleak2b m2d; down=0.5
M1 m1d m1g m1s nmos; right,size=1
M2 m2d m2g m2s nmos; right,size=1
W cs1b lw4b1; down=2.5,color=blue
W lw4b1 lw4b2; right=8,color=blue
W lw4b2 lw4b; up,color=blue
W m1s m2s; right=4
RS m1s rsb; down=2
W c1b rsb; right
W lw3b lw3b1; left=1,color=blue
W lw3b1 lw3b2; down=4,color=blue
W lw3b2 rsb; left=5,color=blue
A1 lw3a2; l={\ \ \ \ \ •}
A2 lw3b; l={\ \ \ \ \ •}
A3 l1a; l={\ \ \ \ \ •}
A4 t1c3; l={\ \ \ \ \ •}
''')
return cct
def test_causal1(self):
a = Circuit()
a.add('V1 1 0 {4 + 2 * u(t)}; down')
a.add('R1 1 2 2; right=2')
a.add('L1 2 3 2; down')
a.add('W 0 3; right')
self.assertEqual(a.sub['s'].is_causal, True, "Causal incorrect")
self.assertEqual2(a.L1.v, 2 * exp(-t) * u(t), "L current incorrect")
def test_in_series(self):
a = Circuit("""
V 1 0 dc
R1 1 2
R2 2 3
R3 3 0
R4 3 4
R5 4 0""")
self.assertEqual(a.in_series('R1'), set(('V', 'R1', 'R2')),
"in_series(R1)")
self.assertEqual(a.in_series('R3'), set(), "in_series(R3)")
self.assertEqual(a.in_series('R4'), set(('R4', 'R5')), "in_series(R4)")
def test_VRL1_ac(self):
"""Lcapy: check VRL circuit at ac
"""
a = Circuit()
a.add('V1 1 0 ac')
a.add('R1 1 2')
a.add('L1 2 0')
self.assertEqual(a.is_ivp, False, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, True, "AC incorrect")
self.assertEqual(a.R1.I, a.L1.I, "currents different")
self.assertEqual(-a.V1.I, a.L1.I, "currents different")
def test_in_parallel(self):
a = Circuit("""
V 1 0 dc
R1 1 0
R2 1 0
R3 1 2
R4 2 0
R5 2 0""")
self.assertEqual(a.in_parallel('R1'), set(('V', 'R1', 'R2')),
"in_parallel(R1)")
self.assertEqual(a.in_parallel('R3'), set(), "in_parallel(R3)")
self.assertEqual(a.in_parallel('R4'), set(('R4', 'R5')),
"in_parallel(R4)")
def test_CCVS1(self):
"""Lcapy: check CCVS
"""
a = Circuit()
a.add('V1 1 0 10')
a.add('R1 1 2 2')
a.add('V2 2 0 0')
a.add('H1 3 0 V2 2')
a.add('R2 3 0 1')
self.assertEqual2(a.R2.V, V(10).Voc, "Incorrect voltage")
def test_VRL1_ac2(self):
"""Lcapy: check VRL circuit at ac for angular frequency 1
"""
a = Circuit()
a.add('V1 1 0 ac 5 0 1')
a.add('R1 1 2 3')
a.add('L1 2 0 4')
self.assertEqual(a.is_ivp, False, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, True, "AC incorrect")
self.assertEqual(a.is_causal, False, "Causal incorrect")
self.assertEqual(a.is_time_domain, False, "Time domain incorrect")
self.assertEqual(a.V1.v, Vt('5*cos(t)'), "V1 voltage incorrect")
self.assertEqual(a.R1.i, It('(4*sin(t)+3*cos(t))/5'), "R1 current incorrect")
def push_pull_lossless_clamp_image():
cct = Circuit()
cct.add('''
P1 p1a p1b; down=3,v=V_{in}
W p1a c1a; right
W p1b c1b; right
C1 c1a c1b; down
W c1a clampret1; right
W clampret1 clampret2; right=4
W clampret2 tf1t5; right
TF1 t1 t2 t3 t4 tapcore _t5 _t6; right
W tf1t5 tf1t52; down
W tf1t52 _t5; right
M2 2d 2g 2s nmos; right
W 2d 2d2; up,fixed
Lleakage2 2d2 t4; up,color=red
M1 1d 1g 1s nmos; right
W 1d 1d2; up,fixed
Lleakage1 1d2 lleak1b; up,color=red
W lleak1b tf1t3a; up
W tf1t3a t3; right=4
''')
# First clamp
cct.add('''
CS1 1d2 cc1b; left=2,color=blue
DS1_A ds1a ls1a; up, color=blue
LS1 ls1a cc1b; up, color=blue
DS1_B cc1b clampret1; up, color=blue
W ds1a ds1a1; down, color=blue
''')
# Second clamp
cct.add('''
CS2 2d2 cc2b; left=2,color=blue
DS2_A ds2a ls2a; up, color=blue
LS2 ls2a cc2b; up, color=blue
DS2_B cc2b clampret2; up, color=blue
W ds2a ds2a1; down, color=blue
''')
cct.add('''
Rs 1s rsb; down
W ds1a1 rsb; right=2
W ds2a1 rsb; left=2
W 1s 2s; right=2
W c1b ds1a1; right
''')
return cct
def test_noisy1(self):
a = Circuit()
a.add('R1 1 0')
a.add('R2 1 0')
an = a.noisy()
b = Circuit()
b.add('R1 1 0 {R1 * R2 / (R1 + R2)}')
bn = b.noisy()
self.assertEqual(an[1].V.n.expr, bn[1].V.n.expr, "Incorrect noise")
def test_VR1_ac2(self):
"""Lcapy: check VR circuit at ac for angular frequency 1
"""
# This can be solved in the time-domain
a = Circuit()
a.add('V1 1 0 ac 5 0 1')
a.add('R1 1 0 1')
self.assertEqual(a.is_ivp, False, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, True, "AC incorrect")
self.assertEqual(a.is_causal, False, "Causal incorrect")
self.assertEqual(a.is_time_domain, True, "Time domain incorrect")
self.assertEqual(a.V1.v, Vt('5*cos(t)'), "V1 voltage incorrect")
self.assertEqual(a.R1.v, Vt('5*cos(t)'), "R1 voltage incorrect")
self.assertEqual(a.V1.i, It('-5*cos(t)'), "V1 current incorrect")
self.assertEqual(a.R1.i, It('5*cos(t)'), "R1 current incorrect")
def test_IV_series(self):
a = Circuit("""
V 2 1 dc
I 1 0 dc
R 2 0""")
self.assertEqual(a.R.v, expr('I * R'), "R voltage incorrect")
self.assertEqual(a.R.i, expr('I'), "R current incorrect")
def test_IV_parallel(self):
a = Circuit("""
V 1 0 dc
I 1 0 dc
R 1 0""")
self.assertEqual(a.R.v, expr('V'), "R voltage incorrect")
self.assertEqual(a.R.i, expr('V / R'), "R current incorrect")
def test_directive(self):
# This has a deliberate empty line.
a = Circuit("""
V 2 0 10
R 2 0 1""")
self.assertEqual(a.R.i, 10, "i incorrect")
def test_RC1(self):
"""Lcapy: check RC network
"""
a = Circuit()
a.add('R1 1 2')
a.add('C1 2 0')
self.assertEqual2(a.Z(1, 2), R('R1').Z, "Z incorrect for R1.")
self.assertEqual2(a.Z(2, 0), C('C1').Z, "Z incorrect for C1.")
self.assertEqual2(
a.Z(1, 0), (R('R1') + C('C1')).Z, "Z incorrect for R1 + C1.")
self.assertEqual2(a.Y(1, 2), R('R1').Y, "Y incorrect for R1.")
self.assertEqual2(a.Y(2, 0), C('C1').Y, "Y incorrect for C1.")
self.assertEqual2(
a.Y(1, 0), (R('R1') + C('C1')).Y, "Y incorrect for R1 + C1.")
self.assertEqual2(a.Isc(1, 0), I(0).Isc, "Isc incorrect")
def forward_topology_image():
cct = Circuit()
# the input (switches-capacitors-transformer)
cct.add('''
P1 p1a p1b; down=5.5,v=V_{in}
W p1a c1a; right
W p1b c1b; right
CIN c1a c1b; down
W c1a dsa; right=2
DS dsb dsa; up=2
W dsb l1a; down
LS l1a l1b; down
W l1b l2b2; down=1.5
W dsa l2a1; right=2
W l2a1 l2b; down=0.5
TF1 l3a l3b l2b l2a tapcore _t5 _t6; right, size=1.5
CS l2a dsb; left,color=gray,v=$V_{Cs}$
A1 l1b; l={\ \ \ \ \ •}
W l2a m1d; down=0.5
M1 m1d m1g m1s nmos; right,size=1
W m1s rsa; down=0.5
RSENSE rsa rsb; down
W rsa rsa1; right,l=$I_{sense}$
W c1b l2b2; right
W l2b2 rsb; right
W l3b l3b1; down
D1 l3a d1b; right=1.5,kind=schottky
W l3b1 d2a; right=1.5
D2 d2a d1b; up,kind=schottky
W d1b loa; right
LO loa lob; right=1.5
W lob lob2; right
CO lob2 cob; down
W lob voa; right
W cob vob; right
P2 voa vob; down,v=V_O
DX loa dxb; down,color=gray
CX dxb cxb; down,color=gray
RX dxb rxb; right,color=gray
W rxb lob; up,color=gray
W d2a cxb; right
W cxb cob; right
''')
return cct
def test_VCCS1(self):
"""Lcapy: check VCCS
"""
a = Circuit()
a.add('V1 1 0 2')
a.add('R1 1 0 1')
a.add('G1 2 0 1 0 3')
a.add('R2 2 0 1')
self.assertEqual2(a.R2.V, V(6).Voc, "Incorrect voltage")
def test_VRC2(self):
"""Lcapy: check VRC circuit with arbitrary s-domain source
"""
a = Circuit()
a.add('V1 1 0 {V(s)}')
a.add('R1 1 2')
a.add('C1 2 0 C1 0')
H = a[2].V.s / a[1].V.s
self.assertEqual2(H, 1 / (s * 'R1' * 'C1' + 1), "Incorrect ratio")
def buck_rectifier_clamp_image():
cct = Circuit()
cct.add('''
P1 d1b d2a; l=from the rectifier, v=$V_{IN}$
W d1b loa; right
LO loa lob; right=1.5
W lob lob2; right
CO lob2 cob; down
W lob voa; right
W cob vob; right
P2 voa vob; down,v=V_O
DX loa dxb; down,color=blue
CX dxb cxb; down,color=blue
RX dxb rxb; right,color=blue
W rxb lob; up,color=blue
W d2a cxb; right
W cxb cob; right
''')
return cct
def push_pull_rcd_snubber_image():
cct = Circuit()
cct.add('''
P1 p1a p1b; down=3,v=V_{in}
W p1a c1a; right
W p1b c1b; right
C1 c1a c1b; down
W c1a tf1t5; right=6
TF1 t1 t2 t3 t4 tapcore _t5 _t6; right, size=1.5
W tf1t5 tf1t52; down
W tf1t52 _t5; right
M2 2d 2g 2s nmos; right
Lleakage2 2d t4; up,color=red
M1 1d 1g 1s nmos; right
Lleakage1 1d lleak1b; up,color=red
W lleak1b tf1t3a; up=1.5
W tf1t3a t3; right=5
''')
# Second snubber
cct.add('''
Csnubber2 2d cc2b; right,color=blue
Dsnubber2 cc2b dc2b; down,color=blue
W cc2b rc2a; right,color=blue
Rsnubber2 rc2a rc2b; down,color=blue
W rc2b dc2b; left,color=blue
''')
# First snubber
cct.add('''
Csnubber1 1d cc1b; right,color=blue
Dsnubber1 cc1b dc1b; down,color=blue
W cc1b rc1a; right,color=blue
Rsnubber1 rc1a rc1b; down,color=blue
W rc1b dc1b; left,color=blue
''')
cct.add('''
W 2s 1s; left=4.5
Rs 1s rsb; down
W c1b rsb; right
W dc1b rsb; left
W dc2b rc1b; left=3.5
''')
return cct
def test_params(self):
a = Circuit("""
R1 1 2;
R2 2 0;
R3 2 3""")
A = a.Aparams(3, 0, 1, 0)
# TODO, FIXME without passing matrix elements through expr
self.assertEqual(expr(A[0, 0]), expr('(R2 + R3) / R2'), "A11")
self.assertEqual(expr(A[0, 1]), expr('R1 + R1 * R3 / R2 + R3'), "A12")
self.assertEqual(expr(A[1, 0]), expr('1 / R2'), "A21")
self.assertEqual(expr(A[1, 1]), expr('(R1 + R2) / R2'), "A22")
Z = a.Zparams(3, 0, 1, 0)
self.assertEqual(expr(Z[0, 0]), expr('R2 + R3'), "Z11")
self.assertEqual(expr(Z[0, 1]), expr('R2'), "Z12")
self.assertEqual(expr(Z[1, 0]), expr('R2'), "Z21")
self.assertEqual(expr(Z[1, 1]), expr('R1 + R2'), "Z22")
def test_kill(self):
a = Circuit("""
V1 1 2 6
V2 2 0 4
R 1 0 2""")
self.assertEqual(a.R.V, 10, "incorrect series voltage")
b = a.kill('V1')
self.assertEqual(b.R.V, 4, "incorrect voltage with V1 killed")
c = a.kill('V2')
self.assertEqual(c.R.V, 6, "incorrect voltage with V2 killed")
d = a.kill_except('V1')
self.assertEqual(d.R.V, 6,
"incorrect voltage with all killed except V1")
def test_RC_ivp(self):
"""Lcapy: check RC IVP"""
a = Circuit("""
C 1 0 C v0
R 1 0""")
self.assertEqual(a.is_ivp, True, "Initial value problem incorrect")
self.assertEqual(a.R.I, -a.C.I, "R + C current different")
self.assertEqual(a.R.V, a.C.V, "R + C voltage different")
self.assertEqual(a.C.I(s), sympify('-v0 / (s * R + 1 / C)'),
"C current wrong")
def test_VRL1_dc3(self):
"""Lcapy: check VRL circuit at dc but with initial conditions
"""
# TODO: This currently fails due to two symbols of the same name
# having different assumptions.
a = Circuit()
a.add('V1 1 0 V1')
a.add('R1 1 2')
a.add('L1 2 0 L1 0')
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
def test_filtered_noise1(self):
"""Lcapy: check circuit filtered noise"""
a = Circuit()
a.add('V1 1 0 noise 3')
a.add('R1 1 2 2')
a.add('C1 2 0 4')
def test_RC1(self):
"""Lcapy: check RC network
"""
a = Circuit()
a.add('R1 1 2')
a.add('C1 2 0')
self.assertEqual2(a.Z(1, 2), R('R1').Z, "Z incorrect for R1.")
self.assertEqual2(a.Z(2, 0), C('C1').Z, "Z incorrect for C1.")
self.assertEqual2(
a.Z(1, 0), (R('R1') + C('C1')).Z, "Z incorrect for R1 + C1.")
self.assertEqual2(a.Y(1, 2), R('R1').Y, "Y incorrect for R1.")
self.assertEqual2(a.Y(2, 0), C('C1').Y, "Y incorrect for C1.")
self.assertEqual2(
a.Y(1, 0), (R('R1') + C('C1')).Y, "Y incorrect for R1 + C1.")
self.assertEqual2(a.Isc(1, 0), I(0).Isc, "Isc incorrect")
def test_VCCS1(self):
"""Lcapy: check VCCS
"""
a = Circuit()
a.add('V1 1 0 2')
a.add('R1 1 0 1')
a.add('G1 2 0 1 0 3')
a.add('R2 2 0 1')
self.assertEqual2(a.R2.V, V(6).Voc, "Incorrect voltage")
def rectifier_rc_snubber_image():
cct = Circuit()
cct.add('''
TF1 l3a l3b l2b l2a tapcore _t5 _t6; right, size=1, l=T
W _t6 t6g; right=0.1, sground
D1 l3a d1b; right=2
D2 l3b d2b; right=2
W l3a cs1a; up,color=blue
W l3b cs2a; down, color=blue
CS1 cs1a cs1b; right, l=$C_S$, color=blue
CS2 cs2a cs2b; right, l=$C_S$, color=blue
RS1 cs1b rs1b; right, l=$R_S$, color=blue
RS2 cs2b rs2b; right, l=$R_S$, color=blue
W d1b rs1b; up, color=blue
W d2b rs2b; down, color=blue
W d2b d1b; up
LO d1b lob; right
CO lob cob; down
W cob cob1; down=0.1, sground
W lob lob2; right, l=Vout
''')
return cct
def test_VRC2(self):
"""Lcapy: check VRC circuit with arbitrary s-domain source
"""
a = Circuit()
a.add('V1 1 0 {V(s)}')
a.add('R1 1 2')
a.add('C1 2 0 C1 0')
H = a[2].V.s / a[1].V.s
self.assertEqual2(H, 1 / (s * 'R1' * 'C1' + 1), "Incorrect ratio")
def test_oneport(self):
a = Circuit("""
V 2 0 s
L 2 1
R 1 0""")
th = a[1].thevenin()
no = a[1].norton()
self.assertEqual(th.Voc, no.Voc, "Voc incorrect")
self.assertEqual(th.Isc, no.Isc, "Isc incorrect")
self.assertEqual(th.Z, no.Z, "Z incorrect")
self.assertEqual(th.Y, no.Y, "Y incorrect")
th = a[2].thevenin(1)
no = a[2].norton(1)
self.assertEqual(th.Voc, no.Voc, "Voc incorrect")
self.assertEqual(th.Isc, no.Isc, "Isc incorrect")
self.assertEqual(th.Z, no.Z, "Z incorrect")
self.assertEqual(th.Y, no.Y, "Y incorrect")
th = a.L.thevenin()
no = a.L.norton()
self.assertEqual(th.Voc, no.Voc, "Voc incorrect")
self.assertEqual(th.Isc, no.Isc, "Isc incorrect")
self.assertEqual(th.Z, no.Z, "Z incorrect")
self.assertEqual(th.Y, no.Y, "Y incorrect")
th = a.thevenin(2, 1)
no = a.norton(2, 1)
self.assertEqual(th.Voc, no.Voc, "Voc incorrect")
self.assertEqual(th.Isc, no.Isc, "Isc incorrect")
self.assertEqual(th.Z, no.Z, "Z incorrect")
self.assertEqual(th.Y, no.Y, "Y incorrect")
def test_VRL1_dc3(self):
"""Lcapy: check VRL circuit at dc but with initial conditions
"""
# TODO: This currently fails due to two symbols of the same name
# having different assumptions.
a = Circuit()
a.add('V1 1 0 V1')
a.add('R1 1 2')
a.add('L1 2 0 L1 0')
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
def test_transfer(self):
"""Lcapy: check transfer function
"""
a = Circuit()
a.add('R1 1 0 1')
a.add('R2 1 2 2')
a.add('C1 2 0 1')
H = a.transfer(1, 0, 2, 0)
self.assertEqual2(H, 1 / (2 * s + 1), "Incorrect transfer function")
h = H.inverse_laplace()
self.assertEqual2(h, exp(-t / 2) * Heaviside(t) / 2,
"Incorrect impulse response")
def test_VRL1_dc2(self):
"""Lcapy: check VRL circuit at dc but with initial conditions
"""
# TODO: This currently fails due to two symbols of the same name
# having different assumptions.
a = Circuit()
a.add('V1 1 0 {V1 + 1}')
a.add('R1 1 2')
a.add('L1 2 0 L1 {(V1 + 1) / R1}')
# This tests if symbols are converted to the defined ones.
self.assertEqual2(a.L1.v, V(0).Voc.s.inverse_laplace(),
"Incorrect time domain voltage")
v = Vs('(V1+1)/s', dc=False).inverse_laplace()
self.assertEqual2(a.R1.v, v,
"Incorrect time domain voltage")
self.assertEqual(a.is_ivp, True, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
def test_VRL1(self):
"""Lcapy: check VRL circuit
"""
a = Circuit()
a.add('V1 1 0 {V1 / s}')
a.add('R1 1 2')
a.add('L1 2 0 L1 0')
# This currently fails due to two symbols of the same name
# having different assumptions.
# Note, V1 acts as a short-circuit for the impedance/admittance
self.assertEqual2(
a.thevenin(1, 2).Voc, a.Voc(1, 2), "incorrect thevenin voltage")
self.assertEqual2(
a.thevenin(1, 2).Z, a.Z(1, 2), "incorrect thevenin impedance")
self.assertEqual2(
a.norton(1, 2).Isc, a.Isc(1, 2), "incorrect norton current")
self.assertEqual2(
a.norton(1, 2).Y, a.Y(1, 2), "incorrect norton admittance")
self.assertEqual2(
a.Z(1, 2), (R('R1') | L('L1')).Z, "Z incorrect across R1")
self.assertEqual2(
a.Z(2, 0), (R('R1') | L('L1')).Z, "Z incorrect across L1")
self.assertEqual2(a.Z(1, 0), R(0).Z, "Z incorrect across V1")
self.assertEqual2(
a.Y(1, 2), (R('R1') | L('L1')).Y, "Y incorrect across R1")
self.assertEqual2(
a.Y(2, 0), (R('R1') | L('L1')).Y, "Y incorrect across L1")
# This has a non-invertible A matrix.
# self.assertEqual2(a.Y(1, 0), R(0).Y, "Y incorrect across V1")
self.assertEqual2(a.Voc(1, 0), V('V1' / s).Voc,
"Voc incorrect across V1")
self.assertEqual(a.is_ivp, True, "Initial value problem incorrect")
self.assertEqual(a.is_dc, False, "DC incorrect")
self.assertEqual(a.is_ac, False, "AC incorrect")
from lcapy import Circuit
import numpy as np
from matplotlib.pyplot import figure, savefig
t = np.linspace(0, 0.01, 1000)
cct = Circuit()
cct.add('V1 1 0 step 10')
cct.add('L1 1 2 0.1')
cct.add('C1 2 3 1e-4')
cct.add('R1 3 0 100')
Vr = cct[3].V
vr = Vr.transient_response(t)
fig = figure()
ax = fig.add_subplot(111)
ax.plot(t, vr, linewidth=2)
ax.set_xlabel('Time (s)')
ax.set_ylabel('Resistor voltage (V)')
ax.grid(True)
savefig('circuit-VRLC3-vr.png')
from lcapy import Circuit, j, f, pi
from numpy import linspace
cct = Circuit()
cct.add('P1 1 0; down')
cct.add('L1 1 2 0.1; right')
cct.add('C1 2 3 1e-3; right')
cct.add('R1 3 4 10; down')
cct.add('W1 0 4; right')
H = cct.transfer(1, 0, 3, 4)
A = H(j * 2 * pi * f)
fv = linspace(0, 100, 400)
A.magnitude.dB.plot(fv)
A.phase.plot(fv)
A.plot(fv, log_scale=True)
def main (argv=None):
if argv is None:
argv = sys.argv
version = __doc__.split('\n')[0]
parser = OptionParser(usage='%prog schematic-file [output-file]', version=version,
description=__doc__)
parser.add_option('--debug', action='store_true',
dest='debug', default=None,
help="enable debugging")
parser.add_option('--draw-nodes', type='str',
dest='draw_nodes', default=None,
help='draw nodes, choice: none, connections, primary, all')
parser.add_option('--nodraw-nodes', action='store_false',
dest='draw_nodes',
help="don't draw nodes")
parser.add_option('--label-nodes', type='str',
dest='label_nodes', default=None,
help='label nodes, choice: none, alpha, pins, primary, all')
parser.add_option('--nolabel-nodes', action='store_false',
dest='label_nodes',
help="don't label nodes")
parser.add_option('--nolabel-ids', action='store_false',
dest='label_ids', default=None,
help="don't label element identifiers")
parser.add_option('--label-ids', action='store_true',
dest='label_ids', default=None,
help="label element identifiers")
parser.add_option('--nolabel-values', action='store_false',
dest='label_values', default=None,
help="don't label values")
parser.add_option('--label-values', action='store_true',
dest='label_values', default=None,
help="labels values")
parser.add_option('--s-model', action='store_true',
dest='s_model', default=False,
help='generate s-domain model schematic')
parser.add_option('--ac-model', action='store_true',
dest='ac_model', default=False,
help='generate AC model schematic')
parser.add_option('--p-model', action='store_true',
dest='p_model', default=False,
help='generate pre-initial model schematic')
parser.add_option('--k-model', action='store_true',
dest='k_model', default=False,
help='generate schematic with independent sources killed')
parser.add_option('--scale', type='float',
dest='scale', default=None,
help='schematic scale factor, this scales the schematic size but not the fonts')
parser.add_option('--node-spacing', type='float',
dest='node_spacing', default=None,
help='this specifies the spacing of the nodes of a component')
parser.add_option('--cpt-size', type='float',
dest='cpt_size', default=None,
help='this specifies the size of a component; it needs to be smaller than node_spacing')
parser.add_option('--help-lines', type='float',
dest='help_lines', default=None,
help="draw help lines")
parser.add_option('--xgraph', action='store_true',
dest='xgraph', default=False,
help="generate graph of component x positions")
parser.add_option('--ygraph', action='store_true',
dest='ygraph', default=False,
help="generate graph of component y positions")
parser.add_option('--stage', type='int',
dest='stage', default=0,
help='graph analysis stage')
parser.add_option('--pdb', action='store_true',
default=False,
help="enter python debugger on exception")
(options, args) = parser.parse_args()
if len(args) < 1:
parser.error('missing argument')
return 1
infilename = args[0]
outfilename = None
if len(args) > 1:
outfilename = args[1]
if options.pdb:
sys.excepthook = schtex_exception
from lcapy import Circuit
cct = Circuit(infilename)
if options.k_model:
cct = cct.kill()
if options.s_model:
cct = cct.s_model()
if options.ac_model:
cct = cct.ac_model()
if options.p_model:
cct = cct.pre_initial_model()
if options.label_nodes not in ('none', 'all', 'alpha', 'pins', 'primary', False, None):
raise ValueError('Illegal option %s for label_nodes' % options.label_nodes)
if options.draw_nodes not in ('none', 'all', 'primary', 'connections',
False, None):
raise ValueError('Illegal option %s for draw_nodes' % options.draw_nodes)
nosave = options.xgraph or options.ygraph
if not options.xgraph and not options.ygraph:
cct.draw(label_nodes=options.label_nodes,
draw_nodes=options.draw_nodes,
label_ids=options.label_ids,
label_values=options.label_values,
filename=outfilename, scale=options.scale,
node_spacing=options.node_spacing, cpt_size=options.cpt_size,
help_lines=options.help_lines, debug=options.debug,
nosave=nosave)
if options.xgraph:
cct.sch.make_graphs()
cct.sch.xgraph.dot(outfilename, stage=options.stage)
return 0
if options.ygraph:
cct.sch.make_graphs()
cct.sch.ygraph.dot(outfilename, stage=options.stage)
return 0
return 0
from lcapy import Circuit
cct = Circuit()
cct.add('V 1 0 step 20')
cct.add('R 1 2 10')
cct.add('C 2 0 1e-4')
# Determine transient response at node 2 evaluated at specified times.
import numpy as np
t = np.linspace(0, 0.01, 1000)
vc = cct[2].v(t)
from matplotlib.pyplot import figure, savefig
fig = figure()
ax = fig.add_subplot(111)
ax.plot(t, vc, linewidth=2)
ax.set_xlabel('Time (s)')
ax.set_ylabel('Capacitor voltage (V)')
ax.grid(True)
savefig('circuit-VRC1-vc.png')
def main (argv=None):
if argv is None:
argv = sys.argv
version = __doc__.split('\n')[0]
parser = OptionParser(usage='%prog schematic-file [output-file]', version=version,
description=__doc__)
parser.add_option('--debug', action='store_true',
dest='debug', default=None,
help="enable debugging")
parser.add_option('--draw-nodes', type='str',
dest='draw_nodes', default=None,
help='draw nodes, choice none, connections, primary, all')
parser.add_option('--nodraw-nodes', action='store_false',
dest='draw_nodes',
help="don't draw nodes")
parser.add_option('--label-nodes', type='str',
dest='label_nodes', default=None,
help='label nodes, choice none, primary, all')
parser.add_option('--nolabel-nodes', action='store_false',
dest='label_nodes',
help="don't label nodes")
parser.add_option('--nolabel-ids', action='store_false',
dest='label_ids', default=None,
help="don't label element identifiers")
parser.add_option('--label-ids', action='store_true',
dest='label_ids', default=None,
help="label element identifiers")
parser.add_option('--nolabel-values', action='store_false',
dest='label_values', default=None,
help="don't label values")
parser.add_option('--label-values', action='store_true',
dest='label_values', default=None,
help="labels values")
parser.add_option('--s-model', action='store_true',
dest='s_model', default=False,
help='generate s-domain model schematic')
parser.add_option('--p-model', action='store_true',
dest='p_model', default=False,
help='generate pre-initial model schematic')
parser.add_option('--k-model', action='store_true',
dest='k_model', default=False,
help='generate schematic with independent sources killed')
parser.add_option('--scale', type='float',
dest='scale', default=1,
help='schematic scale factor')
parser.add_option('--stretch', type='float',
dest='stretch', default=1,
help='schematic stretch factor')
(options, args) = parser.parse_args()
if len(args) < 1:
parser.error('missing argument')
return 1
infilename = args[0]
outfilename = None
if len(args) > 1:
outfilename = args[1]
from lcapy import Circuit
cct = Circuit(infilename)
if options.k_model:
cct = cct.kill()
if options.s_model:
cct = cct.s_model()
if options.p_model:
cct = cct.pre_initial_model()
if options.label_nodes not in ('none', 'all', 'primary', False, None):
raise ValueError('Illegal option %s for label_nodes' % options.label_nodes)
if options.draw_nodes not in ('none', 'all', 'primary', 'connections',
False, None):
raise ValueError('Illegal option %s for draw_nodes' % options.draw_nodes)
cct.draw(label_nodes=options.label_nodes, draw_nodes=options.draw_nodes,
label_ids=options.label_ids, label_values=options.label_values,
filename=outfilename, scale=options.scale, stretch=options.stretch,
debug=options.debug)
return 0
from lcapy import Circuit, t
from matplotlib.pyplot import savefig
from numpy import linspace
cct = Circuit()
cct.add('V1 1 0 step')
cct.add('L1 1 2 L1 0')
cct.add('C1 2 3')
cct.add('R1 3 0')
Vr = cct[3].V
vr = Vr(t)
vr.pprintans('v_R(t)')
vr = vr.subs({'L1':1, 'C1':0.1, 'R1':10, 'V1':1})
if True:
tv = linspace(0, 2, 400)
vr.plot(tv)
savefig('circuit-VRLC2b-vr.png')
from lcapy import Circuit
cct = Circuit()
cct.add('V 1 0 step 10')
cct.add('L 1 2 1e-3')
cct.add('C 2 3 1e-4')
cct.add('R 3 0 10')
import numpy as np
t = np.linspace(0, 0.01, 1000)
vr = cct.R.v(t)
from matplotlib.pyplot import figure, savefig, show
fig = figure()
ax = fig.add_subplot(111)
ax.plot(t, vr, linewidth=2)
ax.set_xlabel('Time (s)')
ax.set_ylabel('Resistor voltage (V)')
ax.grid(True)
show()
savefig('circuit-VRLC1-vr.png')
from lcapy import Circuit
from matplotlib.pyplot import savefig, show
from numpy import linspace
cct = Circuit()
cct.add('V1 1 0 dc')
cct.add('L1 1 2')
cct.add('C1 2 3')
cct.add('R1 3 0')
Vr = cct[3].V
vr = Vr.transient_response()
vr.pprintans('v_R(t)')
if False:
tv = linspace(0, 2, 400)
vr.plot(tv)
show()
savefig('circuit-VRLC2b-vr.png')
