def assign_mul(self, trg_iden, left, right):
res_reg = 4
l_reg = self.loaddd(left, 2)
r_reg = self.loaddd(right, 3)
code = '''
SUB {res} {res}
JZERO {r} ${end}
JODD {l} ${add}
JUMP ${half}
ADD {res} {r}
HALF {l}
ADD {r} {r}
JUMP ${jzero}
'''.format(res=res_reg,
r=r_reg,
l=l_reg,
add=2,
half=2,
end=7,
jzero=(-6))
self.push(code)
if is_arr(trg_iden):
self.store_arr(trg_iden, res_reg)
elif is_variable(trg_iden):
self.store_var(trg_iden, res_reg)
def gen_write(self, node):
_, iden = node
if is_variable(iden):
self.write_variable(iden)
elif is_number(iden):
self.write_number(iden)
elif is_arr(iden):
self.write_arr(iden)
def reserve_memory(self, symtab):
for iden in symtab:
if is_variable(iden):
self.memory[iden[1]] = self.mem_id
self.mem_id += 1
for iden in symtab:
if is_arr(iden):
self.memory[iden[1]] = self.mem_id
self.mem_id += iden[3] - iden[2] + 1
def loaddd(self, iden, trg_reg):
if is_number(iden):
self.gen_number(iden, trg_reg)
return trg_reg
elif is_variable(iden):
iden_reg = self.check_in_regs(iden[1])
if not iden_reg:
iden_mem_id = self.memory[iden[1]]
self.gen_number(iden_mem_id)
self.push('LOAD {}'.format(trg_reg))
else:
self.push('COPY {} {}'.format(trg_reg, iden_reg))
return trg_reg
elif is_arr(iden):
_, name, inner, _ = iden
if is_number(inner):
offset = inner + self.arr_offset(iden)
self.gen_number(offset)
self.push('LOAD {}'.format(trg_reg))
return trg_reg
elif is_declared_var(inner, self.symtab):
inner_reg = self.check_in_regs(inner)
if not inner_reg:
inner_mem_id = self.memory[inner]
self.gen_number(inner_mem_id, 0)
self.push('''
LOAD 1
''')
offset = self.arr_offset(iden)
self.gen_number(offset, 0)
self.push('''
ADD 0 1
LOAD {}
'''.format(trg_reg))
return trg_reg
else:
offset = self.arr_offset(iden)
self.gen_number(offset, 0)
self.push('''
ADD {} {}
LOAD {}
'''.format(0, inner_reg, trg_reg))
return trg_reg
elif is_declared_var(iden, self.symtab):
iden_reg = self.check_in_regs(iden)
if not iden_reg:
iden_mem_id = self.memory[iden]
self.gen_number(iden_mem_id)
self.push('LOAD {}'.format(trg_reg))
else:
self.push('COPY {} {}'.format(trg_reg, iden_reg))
return trg_reg
pass
def assign_minus(self, trg_iden, left, right):
l_reg = self.loaddd(left, 2)
r_reg = self.loaddd(right, 3)
self.push('''
SUB {l} {r}
'''.format(l=l_reg, r=r_reg))
if is_arr(trg_iden):
self.store_arr(trg_iden, l_reg)
elif is_variable(trg_iden):
self.store_var(trg_iden, l_reg)
def assign_simple_expr(self, trg_iden, expr):
_, right = expr
if is_arr(trg_iden):
val_reg = self.loaddd(right, 3)
self.loaddd(trg_iden[2], 2)
self.gen_number(self.arr_offset(trg_iden))
self.push('''
ADD {a} {inner}
STORE {val}
'''.format(a=0, inner=2, val=val_reg))
return
val_reg = self.loaddd(right, 1)
self.store_var(trg_iden, 1)
def assign_plus(self, trg_iden, left, right):
if is_arr(trg_iden):
l_reg = self.loaddd(left, 2)
r_reg = self.loaddd(right, 3)
self.push('''
ADD {l} {r}
'''.format(l=l_reg, r=r_reg))
self.store_arr(trg_iden, l_reg)
return
l_reg = self.loaddd(left, 2)
r_reg = self.loaddd(right, 3)
self.push('''
ADD {l} {r}
'''.format(l=l_reg, r=r_reg))
self.store_var(trg_iden, l_reg)
def assign_mod(self, trg_iden, left, right):
l_reg = self.loaddd(left, 2)
r_reg = self.loaddd(right, 3)
res_reg = 4
divide = '''
COPY {res} {l}
JZERO {r} ${end}
COPY 1 {r}
COPY {res} 1
SUB {res} {l}
JZERO {res} ${body}
JUMP ${out}
ADD 1 1
JUMP ${loop}
SUB {res} {res}
COPY 0 1
SUB 0 {l}
JZERO 0 ${add}
ADD {res} {res}
HALF 1
JUMP ${check}
ADD {res} {res}
INC {res}
SUB {l} 1
HALF 1
COPY 0 {r}
SUB 0 1
JZERO 0 ${loop2}
JUMP ${out2}
SUB {l} {l}
SUB {res} {res}
'''.format(res=res_reg,
l=l_reg,
r=r_reg,
end=23,
body=2,
out=3,
loop=-5,
add=4,
check=5,
loop2=-12,
out2=3)
self.push(divide)
if is_arr(trg_iden):
self.store_arr(trg_iden, l_reg)
elif is_variable(trg_iden):
self.store_var(trg_iden, l_reg)
def gen_read(self, node):
_, iden = node
if is_variable(iden):
self.read_variable(iden)
elif is_arr(iden):
self.read_array(iden)
