def __init__(self, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = cyc1000.Platform()
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
# self.add_csr("leds", allow_user_defined=True)
# self.submodules.leds = ClassicLed(platform.request("user_led", 0))
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, sdram_rate="1:1", **kwargs):
platform = easyfpga.Platform()
# Limit internal rom and sram size
kwargs["integrated_rom_size"] = 0x6200
kwargs["integrated_sram_size"] = 0x1000
# Can only support minimal variant of vexriscv
if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
kwargs["cpu_variant"] = "minimal"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on RZ-EasyFPGA",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = MT48LC4M16(sys_clk_freq, sdram_rate), # Hynix HY57V641620FTP-7
l2_cache_size = 0
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1",
with_led_chaser=True, **kwargs):
platform = tec0117.Platform()
# Disable Integrated ROM.
kwargs["integrated_rom_size"] = 0
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on TEC0117",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W74M64FV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W74M64FV(Codes.READ_1_1_4), with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.bus.regions["spiflash"].origin + bios_flash_offset,
size = 32*kB,
linker = True)
)
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL.
self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk)
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
l2_cache_size = 128,
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=int(25e6), sdram_rate="1:1",
with_led_chaser=True, **kwargs):
platform = tec0117.Platform()
# Put BIOS in SPIFlash to save BlockRAMs.
kwargs["integrated_rom_size"] = 0
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on TEC0117",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="4x", dummy_cycles=6)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 64*kB,
linker = True)
)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
sdram_clk = ClockSignal("sys2x" if sdram_rate == "1:2" else "sys") # FIXME: use phase shift from PLL.
self.specials += DDROutput(0, 1, sdram_pads.clk, sdram_clk)
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
l2_cache_size = 128,
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = max1000.Platform(device)
# SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
# integrated_rom_size=0x8000,
# **kwargs)
# csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
SoCSDRAM.__init__(
self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x6000,
# integrated_main_ram_size=0x4000,
**kwargs)
self.mem_map['spiflash'] = 0x20000000
spiflash_pads = platform.request('spiflash')
self.add_memory_region("spiflash", self.mem_map["spiflash"],
8 * 1024 * 1024)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=8,
div=4,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
#self.spiflash.add_clk_primitive("xc7");
# 8 MB flash: W74M64FVSSIQ
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'])
# spi_flash.py supports max 16MB linear space
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
self.add_csr("leds", allow_user_defined=True)
self.submodules.leds = ClassicLed(platform.request("user_led", 0))
# self.add_csr("gpio_leds", allow_user_defined=True)
self.add_csr("gpio_leds", allow_user_defined=True)
self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, device, sys_clk_freq=int(50e6), **kwargs):
assert sys_clk_freq == int(50e6)
platform = max1000.Platform(device)
SoCSDRAM.__init__(self,
platform,
clk_freq=sys_clk_freq,
integrated_rom_size=0x6000,
**kwargs)
self.mem_map['spiflash'] = 0x20000000
spiflash_pads = platform.request('spiflash')
self.add_memory_region("spiflash", self.mem_map["spiflash"],
8 * 1024 * 1024)
self.submodules.spiflash = SpiFlash(spiflash_pads,
dummy=8,
div=4,
endianness=self.cpu.endianness)
self.add_csr("spiflash")
# 8 MB flash: W74M64FVSSIQ
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
self.add_constant("FLASH_BOOT_ADDRESS", self.mem_map['spiflash'])
# spi_flash.py supports max 16MB linear space
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]),
self.spiflash.bus)
self.submodules.crg = _CRG(platform)
# self.submodules.leds = ClassicLed(Cat(platform.request("user_led", i) for i in range(7)))
self.add_csr("leds", allow_user_defined=True)
self.submodules.leds = ClassicLed(platform.request("user_led", 0))
#
# self.add_csr("gpio_leds", allow_user_defined=True)
# self.submodules.gpio_leds = gpio.GPIOOut(platform.request("gpio_leds"))
# use micron device as winbond and ISSI not available
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
sdram_module = MT48LC4M16(self.clk_freq, "1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# include all unused pins as generic BBIO basic IP core
bbio_pads = platform.request("bbio")
# we can exclue any number of I/O pins to be included
self.submodules.bbio = bbioBasic(bbio_pads, exclude=None)
self.add_wb_slave(mem_decoder(self.mem_map["bbio"]), self.bbio.bus)
self.add_memory_region("bbio", self.mem_map["bbio"], 4 * 4 * 1024)
def __init__(self,
bios_flash_offset,
sys_clk_freq=int(25e6),
sdram_rate="1:1",
**kwargs):
platform = tec0117.Platform()
# Use custom default configuration to fit in LittleBee.
kwargs["integrated_sram_size"] = 0x1000
kwargs["integrated_rom_size"] = 0x6000
kwargs["cpu_type"] = "vexriscv"
kwargs["cpu_variant"] = "lite"
# Set CPU variant / reset address
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on TEC0117",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
# FIXME: SPI Flash does not seem responding, power down set after loading bitstream?
#self.bus.add_region("rom", SoCRegion(
# origin = self.mem_map["spiflash"] + bios_flash_offset,
# size = 32*kB,
# linker = True)
#)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
self.comb += sdram_pads.clk.eq(
~ClockSignal("sys")) # FIXME: use phase shift from PLL.
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
self.add_sdram(
"sdram",
phy=self.sdrphy,
module=MT48LC4M16(sys_clk_freq, sdram_rate), # FIXME.
l2_cache_size=128,
l2_cache_min_data_width=256,
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
