def flash(build_dir, build_name, bios_flash_offset): from litex.build.dfu import DFUProg prog = DFUProg(vid="1209", pid="5bf0") bitstream = open(f"{build_dir}/gateware/{build_name}.bin", "rb") bios = open(f"{build_dir}/software/bios/bios.bin", "rb") image = open(f"{build_dir}/image.bin", "wb") # Copy bitstream at 0. assert bios_flash_offset >= 128 * kB for i in range(0, bios_flash_offset): b = bitstream.read(1) if not b: image.write(0xff.to_bytes(1, "big")) else: image.write(b) # Copy bios at bios_flash_offset. for i in range(0, 32 * kB): b = bios.read(1) if not b: image.write(0xff.to_bytes(1, "big")) else: image.write(b) bitstream.close() bios.close() image.close() prog.load_bitstream(f"{build_dir}/image.bin")
def main(): from litex.soc.integration.soc import LiteXSoCArgumentParser parser = LiteXSoCArgumentParser(description="LiteX SoC on iCEBreaker") target_group = parser.add_argument_group(title="Target options") target_group.add_argument("--build", action="store_true", help="Build bitstream.") target_group.add_argument("--flash", action="store_true", help="Flash bitstream and BIOS.") target_group.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.") target_group.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.") target_group.add_argument("--revision", default="v1", help="Board revision (v0 or v1).") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC( bios_flash_offset = int(args.bios_flash_offset, 0), sys_clk_freq = int(float(args.sys_clk_freq)), revision = args.revision, **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.flash: from litex.build.dfu import DFUProg prog_gw = DFUProg(vid="1d50", pid="0x6146", alt=0) prog_sw = DFUProg(vid="1d50", pid="0x6146", alt=1) prog_gw.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".bin"), reset=False) # FIXME prog_sw.load_bitstream(builder.get_bios_filename())
def flash(bios_flash_offset): from litex.build.dfu import DFUProg prog = DFUProg(vid="1209", pid="5bf0") bitstream = open("build/fomu_pvt/gateware/fomu_pvt.bin", "rb") bios = open("build/fomu_pvt/software/bios/bios.bin", "rb") image = open("build/fomu_pvt/image.bin", "wb") # Copy bitstream at 0x00000000 for i in range(0x00000000, 0x0020000): b = bitstream.read(1) if not b: image.write(0xff.to_bytes(1, "big")) else: image.write(b) # Copy bios at 0x00020000 for i in range(0x00000000, 0x00010000): b = bios.read(1) if not b: image.write(0xff.to_bytes(1, "big")) else: image.write(b) bitstream.close() bios.close() image.close() prog.load_bitstream("build/fomu_pvt/image.bin")
def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--flash", action="store_true", help="Flash bitstream and BIOS.") parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency.") parser.add_argument("--bios-flash-offset", default="0xa0000", help="BIOS offset in SPI Flash.") parser.add_argument("--revision", default="v1", help="Board revision (v0 or v1).") builder_args(parser) soc_core_args(parser) args = parser.parse_args() soc = BaseSoC(bios_flash_offset=int(args.bios_flash_offset, 0), sys_clk_freq=int(float(args.sys_clk_freq)), revision=args.revision, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) if args.flash: from litex.build.dfu import DFUProg prog_gw = DFUProg(vid="1d50", pid="0x6146", alt=0) prog_sw = DFUProg(vid="1d50", pid="0x6146", alt=1) prog_gw.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bin"), reset=False) prog_sw.load_bitstream( os.path.join(builder.software_dir, 'bios/bios.bin'))
def create_programmer(self): return DFUProg(vid="1209", pid="5af0")
def create_programmer(self): return DFUProg(vid="1d50", pid="6130")