def main(): parser = argparse.ArgumentParser(description="PCIe Screamer Test Gateware") parser.add_argument("--m2", action="store_true", help="use M2 variant of PCIe Screamer") parser.add_argument("--with-analyzer", action="store_true", help="enable Analyzer") parser.add_argument("--with-loopback", action="store_true", help="enable USB Loopback") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") args = parser.parse_args() if args.m2: from platforms.pcie_screamer_m2 import Platform else: from platforms.pcie_screamer import Platform platform = Platform() soc = PCIeScreamer(platform, args.with_analyzer, args.with_loopback) builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv") builder.build(run=args.build) if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg") prog.load_bitstream("build/gateware/top.bit") if args.flash: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, "build/gateware/top.bin")
def flash(self): flash_regions = { "buildroot/Image.fbi": "0x00000000", # Linux Image: copied to 0xc0000000 by bios "buildroot/rootfs.cpio.fbi": "0x00500000", # File System: copied to 0xc0800000 by bios "buildroot/rv32.dtb.fbi": "0x00d00000", # Device tree: copied to 0xc1000000 by bios "emulator/emulator.bin.fbi": "0x00e00000", # MM Emulator: copied to 0xc1100000 by bios } from litex.build.openocd import OpenOCD prog = OpenOCD("prog/openocd_xilinx.cfg", flash_proxy_basename="bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") for filename, base in flash_regions.items(): base = int(base, 16) print("Flashing {} at 0x{:08x}".format(filename, base)) prog.flash(base, filename)
def create_programmer(self, **kwargs): # For xc3sprog # See also http://xc3sprog.sourceforge.net # get source with: svn checkout https://svn.code.sf.net/p/xc3sprog/code/trunk xc3sprog if self.programmer == "xc3sprog": # to program the configuration flash, the FPGA must first be # programmed with a bitstream which provides a way to foward # data to flash. This is called a "flash proxy". Flash proxies # for some parts are already included in xc3sprog. Additional # ones can be found e.g. https://github.com/quartiq/bscan_spi_bitstreams # defines which flash proxy bitstream to use for which part flash_proxy = { "s7-50": "bscan_spi_xc7s50.bit", "s7-25": "bscan_spi_xc7s25.bit" }[self.device_variant] programmer = XC3SProg("jtaghs1_fast", flash_proxy_basename=flash_proxy) # search part where to find proxy bitsreams. If not specified # defaults to one of: # "~/.migen", "/usr/local/share/migen", "/usr/share/migen", # "~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs", # "~/.litex", "/usr/local/share/litex", "/usr/share/litex" programmer.set_flash_proxy_dir("prog") return programmer # For Xilinx Vivado programmer # Vivado also uses flash proxy bitstreams but they are already shipped # with Vivado and are used automatically. Flash_part specifies the # exact part used in the Arty-S7 Rev. E elif self.programmer == "vivado": return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4") # For OpenOCD elif self.programmer == "openocd": bscan_spi = "bscan_spi_xc7s50.bit" \ if "xc7s50" in self.device \ else "bscan_spi_xc7a25.bit" programmer = OpenOCD("openocd_xilinx.cfg", bscan_spi) programmer.set_flash_proxy_dir("prog") return programmer else: raise ValueError("{} programmer is not supported".format( self.programmer))
def main(): parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv") parser.add_argument("--build", action="store_true", help="build bitstream") parser.add_argument("--load", action="store_true", help="load bitstream (SRAM)") parser.add_argument("--flash", action="store_true", help="flash bitstream (SPI Flash)") args = parser.parse_args() if args.build: soc = LinuxSoC() builder = Builder(soc, output_dir="build") builder.build() if args.load: from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd_xilinx.cfg") prog.load_bitstream("build/gateware/top.bit") if args.flash: flash_regions = { "build/gateware/top.bin": "0x00000000", # FPGA image: automatically loaded at startup "binaries/Image": "0x00400000", # Linux Image: copied to 0xc0000000 by bios "binaries/rootfs.cpio": "0x00800000", # File System: copied to 0xc2000000 by bios "binaries/rv32.dtb": "0x00f00000", # Device tree: copied to 0xc3000000 by bios "emulator/emulator.bin": "0x00f80000", # MM Emulator: copied to 0x20000000 by bios } from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd_xilinx.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") for filename, base in flash_regions.items(): base = int(base, 16) print("Flashing {} at 0x{:08x}".format(filename, base)) prog.flash(base, filename)
class XilinxOCDProgrammer(): def __init__(self, soc): openocddir = os.path.join(os.environ["ZTC_TOOLS_DIR"], "share", "openocd") cfg = os.path.join(openocddir, "openocd_xilinx.cfg") device = soc.platform.device.split("-", 1)[0] if device == "xc7a35ticsg324": device = "xc7a35t" flash_proxy = os.path.join("bscan_spi_bitstreams", "bscan_spi_" + device + ".bit") self.prog = OpenOCD(cfg, flash_proxy_basename=flash_proxy) self.prog.set_flash_proxy_dir(openocddir) def load(self, bitstream_file): self.prog.load_bitstream(bitstream_file) def flash(self, regions): for _, item in regions.items(): print("Flashing {} at 0x{:08x}".format(item[0], item[2])) self.prog.flash(item[2], item[0])
#!/usr/bin/env python3 from litex.build.openocd import OpenOCD prog = OpenOCD("openocd.cfg", flash_proxy_basename="bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0x0, "build/gateware/top.bin")
def _prog_fpga_flash(filename): from litex.build.openocd import OpenOCD prog = OpenOCD("openocd/openocd.cfg", flash_proxy_basename="openocd/bscan_spi_xc7a35t.bit") prog.set_flash_proxy_dir(".") prog.flash(0, filename)