def main():
parser = argparse.ArgumentParser(
description="LiteDRAM standalone core generator")
builder_args(parser)
parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file")
parser.add_argument("--sim",
action='store_true',
help="Integrate SDRAMPHYModel in core for simulation")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if "clk_freq" in k:
core_config[k] = float(core_config[k])
if k == "sdram_module":
core_config[k] = getattr(litedram_modules, core_config[k])
if k == "sdram_phy":
core_config[k] = getattr(litedram_phys, core_config[k])
# Generate core --------------------------------------------------------------------------------
if args.sim:
platform = SimPlatform("", io=[])
elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
platform = LatticePlatform(
"LFE5UM5G-45F-8BG381C", io=[],
toolchain="trellis") # FIXME: allow other devices.
elif core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
elif core_config["sdram_phy"] in [
litedram_phys.USDDRPHY, litedram_phys.USPDDRPHY
]:
platform = XilinxPlatform("", io=[], toolchain="vivado")
else:
raise ValueError("Unsupported SDRAM PHY: {}".format(
core_config["sdram_phy"]))
builder_arguments = builder_argdict(args)
builder_arguments["compile_gateware"] = False
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
builder = Builder(soc, **builder_arguments)
builder.build(build_name="litedram_core", regular_comb=False)
if soc.cpu_type is not None:
init_filename = "mem.init"
os.system("mv {} {}".format(
os.path.join(builder.gateware_dir, init_filename),
os.path.join(builder.gateware_dir, "litedram_core.init"),
))
replace_in_file(os.path.join(builder.gateware_dir, "litedram_core.v"),
init_filename, "litedram_core.init")
def __init__(self, io, clocks: Clocks):
common_io = [
("sys_rst", 0, Pins(1)),
(
"serial",
0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
]
clocks.add_io(common_io)
SimPlatform.__init__(self, "SIM", common_io + io)
def __init__(self, **kwargs):
# Setting sys_clk_freq too low will cause wishbone timeouts !!!
sys_clk_freq = int(20e6)
print(kwargs)
SoCCore.__init__(self,
SimPlatform("SIM", _io),
clk_freq=sys_clk_freq,
integrated_rom_size=0,
integrated_sram_size=0,
ident="LiteX Simulation",
ident_version=True,
with_uart=False,
**kwargs)
# crg
self.submodules.crg = CRG(self.platform.request("sys_clk"))
# ----------------------------
# Virtual serial to Wishbone bridge
# ----------------------------
# bridge virtual serial phy as wishbone master
self.submodules.uart_phy = RS232PHYModel(
self.platform.request("serial"))
self.submodules.uartbone = \
Stream2Wishbone(self.uart_phy, clk_freq=self.clk_freq)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
def __init__(self, name, io):
SimPlatform.__init__(self, name, io)
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
),
),
# Wishbone
("wishbone", 0, Subsignal("adr", Pins(30)), Subsignal("dat_r", Pins(32)),
Subsignal("dat_w",
Pins(32)), Subsignal("sel", Pins(4)), Subsignal("cyc", Pins(1)),
Subsignal("stb", Pins(1)), Subsignal("ack",
Pins(1)), Subsignal("we", Pins(1)),
Subsignal("cti", Pins(3)), Subsignal("bte",
Pins(2)), Subsignal("err", Pins(1))),
]
build_dir = "/workdir/build/liteeth"
platform = SimPlatform("SIM", _io)
core_config = {
'clk_freq': 125000000,
'core': 'wishbone',
'endianness': 'big',
'soc': {
'mem_map': {
'ethmac': 805306368
}
}
}
class ModelMACCore(SoCMini):
"""This is a rough conglomeration of the LiteX eth MACCore and the
def __init__(self,
toolchain="vivado",
sys_clk_freq=int(100e6),
args=None,
ip_address="192.168.100.50",
mac_address=0x10e2d5000001,
udp_port=1234,
**kwargs):
if not args.sim:
platform = arty.Platform(toolchain=toolchain)
else:
platform = SimPlatform("SIM", _io)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Arty A7",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
if not args.sim:
self.submodules.crg = _CRG(platform, sys_clk_freq, args)
else:
self.submodules.crg = CRG(platform.request("sys_clk"))
# DDR3 SDRAM -------------------------------------------------------------------------------
if not args.sim:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
else:
from litedram.gen import get_dram_ios
core_config = dict()
core_config["sdram_module_nb"] = 2 # Number of byte groups
core_config["sdram_rank_nb"] = 1 # Number of ranks
core_config['sdram_module'] = getattr(litedram_modules,
'MT41K128M16')
core_config["memtype"] = "DDR3" # DRAM type
platform.add_extension(get_dram_ios(core_config))
sdram_module = core_config["sdram_module"](
sys_clk_freq,
rate={
"DDR2": "1:2",
"DDR3": "1:4",
"DDR4": "1:4"
}[core_config["memtype"]])
from litex.tools.litex_sim import get_sdram_phy_settings
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
phy_settings = get_sdram_phy_settings(
memtype=sdram_module.memtype,
data_width=core_config["sdram_module_nb"] * 8,
clk_freq=sdram_clk_freq)
self.submodules.ddrphy = SDRAMPHYModel(
module=sdram_module,
settings=phy_settings,
clk_freq=sdram_clk_freq,
verbosity=3,
)
class ControllerDynamicSettings(Module, AutoCSR, AutoDoc):
"""Allows to change LiteDRAMController behaviour at runtime"""
def __init__(self):
self.refresh = CSRStorage(
reset=1,
description="Enable/disable Refresh commands sending")
self.submodules.controller_settings = ControllerDynamicSettings()
self.add_csr("controller_settings")
controller_settings = ControllerSettings()
controller_settings.with_auto_precharge = True
controller_settings.with_refresh = self.controller_settings.refresh.storage
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=0,
l2_cache_min_data_width=0, #128
l2_cache_reverse=True,
controller_settings=controller_settings)
# Ethernet / Etherbone ---------------------------------------------------------------------
if not args.sim:
# Ethernet PHY (arty)
self.submodules.ethphy = LiteEthPHYMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
udp_port=udp_port)
else:
# Ethernet PHY (simulation)
self.submodules.ethphy = LiteEthPHYModel(
self.platform.request("eth", 0)) # FIXME
self.add_csr("ethphy")
# Ethernet Core
ethcore = LiteEthUDPIPCore(self.ethphy,
ip_address=ip_address,
mac_address=mac_address,
clk_freq=sys_clk_freq)
self.submodules.ethcore = ethcore
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp,
udp_port,
mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
if args.sim:
self.comb += platform.trace.eq(1)
# Rowhammer --------------------------------------------------------------------------------
self.submodules.rowhammer_dma = LiteDRAMDMAReader(
self.sdram.crossbar.get_port())
self.submodules.rowhammer = RowHammerDMA(self.rowhammer_dma)
self.add_csr("rowhammer")
def add_xram(self, name, origin, mem, mode='rw'):
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc import SoCRegion
ram = wishbone.SRAM(mem,
bus=wishbone.Interface(data_width=mem.width),
read_only='w' not in mode)
ram_bus = wishbone.Interface(data_width=self.bus.data_width)
self.submodules += wishbone.Converter(ram_bus, ram.bus)
region = SoCRegion(origin=origin,
size=mem.width // 8 * mem.depth,
mode=mode)
self.bus.add_slave(name, ram_bus, region)
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name), colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
# Bist -------------------------------------------------------------------------------------
if not args.no_memory_bist:
# ------------------------------ writer ------------------------------------
dram_wr_port = self.sdram.crossbar.get_port()
self.submodules.writer = Writer(dram_wr_port)
self.add_csr('writer')
# TODO: Rename as 'pattern_wr_w?'
add_xram(self,
name='pattern_w0',
mem=self.writer.memory_w0,
origin=0x20000000)
add_xram(self,
name='pattern_w1',
mem=self.writer.memory_w1,
origin=0x21000000)
add_xram(self,
name='pattern_w2',
mem=self.writer.memory_w2,
origin=0x22000000)
add_xram(self,
name='pattern_w3',
mem=self.writer.memory_w3,
origin=0x23000000)
add_xram(self,
name='pattern_adr',
mem=self.writer.memory_adr,
origin=0x24000000)
# ----------------------------- reader -------------------------------------
dram_rd_port = self.sdram.crossbar.get_port()
self.submodules.reader = Reader(dram_rd_port)
self.add_csr('reader')
add_xram(self,
name='pattern_rd_w0',
mem=self.reader.memory_w0,
origin=0x30000000)
add_xram(self,
name='pattern_rd_w1',
mem=self.reader.memory_w1,
origin=0x31000000)
add_xram(self,
name='pattern_rd_w2',
mem=self.reader.memory_w2,
origin=0x32000000)
add_xram(self,
name='pattern_rd_w3',
mem=self.reader.memory_w3,
origin=0x33000000)
add_xram(self,
name='pattern_rd_adr',
mem=self.reader.memory_adr,
origin=0x34000000)
# Payload executor -------------------------------------------------------------------------
if not args.no_payload_executor:
# TODO: disconnect bus during payload execution
phy_settings = self.sdram.controller.settings.phy
scratchpad_width = phy_settings.dfi_databits * phy_settings.nphases
scratchpad_size = 2**10
payload_mem = Memory(32, 2**10)
scratchpad_mem = Memory(scratchpad_width,
scratchpad_size // (scratchpad_width // 8))
self.specials += payload_mem, scratchpad_mem
add_xram(self, name='payload', mem=payload_mem, origin=0x35000000)
add_xram(self,
name='scratchpad',
mem=scratchpad_mem,
origin=0x36000000,
mode='r')
self.submodules.payload_executor = PayloadExecutor(
mem_payload=payload_mem,
mem_scratchpad=scratchpad_mem,
dfi=self.sdram.dfii.ext_dfi,
dfi_sel=self.sdram.dfii.ext_dfi_sel,
nranks=self.sdram.controller.settings.phy.nranks,
bankbits=self.sdram.controller.settings.geom.bankbits,
rowbits=self.sdram.controller.settings.geom.rowbits,
colbits=self.sdram.controller.settings.geom.colbits,
rdphase=self.sdram.controller.settings.phy.rdphase,
)
self.payload_executor.add_csrs()
self.add_csr('payload_executor')
