def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 1, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 2, loose=True), 1e9/300e6)
self.add_period_constraint(self.lookup_request("clk300", 3, loose=True), 1e9/300e6)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# DDR4 memory channel C1 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 61]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 62]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 63]")
# DDR4 memory channel C2 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 67]")
# DDR4 memory channel C3 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 71]")
# DDR4 memory channel C4 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 72]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 73]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 74]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command(
"set_property -dict { BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE "
"BITSTREAM.GENERAL.COMPRESS TRUE } [current_design]")
# Clock constraint
for id in range(0, 4):
_clk = self.lookup_request("sys_clk", id, loose=True)
self.add_period_constraint(_clk, _clk.platform_info['freq_hz'])
self.add_platform_command(
"set_property INTERNAL_VREF 0.84 [get_iobanks 40]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 41]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 42]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 65]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 66]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 67]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 46]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 47]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 48]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 70]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 71]",
"set_property INTERNAL_VREF 0.84 [get_iobanks 72]",
)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("sysclk", 0, loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("sysclk", 1, loose=True), 1e9/100e6)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# DDR4 memory channel C0 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
# DDR4 memory channel C1 Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 68]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 69]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
# Other suggested configurations
self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")
self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]")
self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]")
# For HBM2 IP in Vivado 2019.2 (https://www.xilinx.com/support/answers/72607.html)
self.add_platform_command("connect_debug_port dbg_hub/clk [get_nets apb_clk]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command(
"""create_clock -name s7pciephy_pcie_clk -period 10 [get_nets pcie_x2_clk_p]"""
)
from gateware import constraints
constraints.apply_xilinx_pcie_constraints(self)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True),
1e9 / 200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True),
1e9 / 156e6)
self.add_period_constraint(
self.lookup_request("sgmii_clock", loose=True), 1e9 / 125e6)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(
self.lookup_request("clk200").p, 1e9 / 200e6)
except ConstraintError:
pass
try:
self.add_period_constraint(
self.lookup_request("sgmii_clock").p, 1e9 / 125e6)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
if isinstance(self.toolchain, XilinxISEToolchain):
self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
else:
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
except ConstraintError:
pass
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 46]")
