def main():
parser = argparse.ArgumentParser(description="SDRAM Loopback SoC on Marble*")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--ip", default="192.168.19.70",
help="Assign an ip address")
parser.add_argument("--ethernet-phy", default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p", "--program-only", action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build", action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true",
help="program FPGA")
parser.add_argument("--threads", default=4,
help="set number of threads (default=4)")
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
parser.add_argument("-s", "--sim", action="store_true",
help="Simulate")
args = parser.parse_args()
if args.sim:
soc_kwargs = soc_core_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
soc_kwargs["integrated_main_ram_size"] = 0x10000
soc_kwargs = soc_core_argdict(args)
soc_kwargs["uart_name"] = "sim"
# sim_config.add_module("serial2console", "serial")
sim_config.add_module(
'ethernet',
"eth",
args={"interface": "xxx1",
"ip": "192.168.88.101",
"vcd_name": "foo.vcd"})
soc = SDRAMSimSoC(phy="rgmii",
with_ethernet=True,
with_etherbone=True,
with_sdram=True,
etherbone_ip_address="192.168.88.50",
etherbone_mac_address=0x12345678abcd,
**soc_kwargs)
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(
threads=args.threads,
trace=args.trace,
sim_config=sim_config)
kwargs = soc_core_argdict(args)
# soc = SDRAMLoopbackSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs)
soc = SDRAMDevSoC(ip=args.ip, phy=args.ethernet_phy, **kwargs)
builder = Builder(soc, **builder_argdict(args))
builder.build()
if args.load:
prog = marble.Platform().create_programmer()
prog.load_bitstream(os.path.join("build", "marble", "gateware", "marble.bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on MarbleMini")
builder_args(parser)
soc_sdram_args(parser)
# soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="select Ethernet PHY (rgmii or 1000basex)")
args = parser.parse_args()
if args.with_ethernet:
soc = LTCSocDev(phy=args.ethernet_phy, **soc_sdram_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_sdram_argdict(args))
# soc = EthernetSoC(phy=args.ethernet_phy, **soc_core_argdict(args))
else:
soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
if not args.program_only:
vns = builder.build()
if False:
soc.analyzer.do_exit(vns)
prog = soc.platform.create_programmer()
import os
prog.load_bitstream(os.path.join(builder.gateware_dir, "marblemini.bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--sys-clk-freq", type=float, default=48e6, help="Select system clock frequency")
parser.add_argument("--document-only", action="store_true", help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Leech")
parser.add_argument("--sys-clk-freq",
type=float,
default=48e6,
help="Select system clock frequency")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software: we don't have CPU.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
def main():
parser = argparse.ArgumentParser(
description="SDRAM Loopback SoC on Marble*")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build",
action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true", help="program FPGA")
args = parser.parse_args()
if args.build:
soc = SDRAMLoopbackSoC(with_ethernet=args.with_ethernet,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(run=not args.program_only)
if args.load:
prog = kc705.Platform().create_programmer()
prog.load_bitstream(
os.path.join("build", "kc705", "gateware", "kc705.bit"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--seed", default=0, help="seed to use in nextpnr")
parser.add_argument("--placer",
default="heap",
choices=["sa", "heap"],
help="which placer to use in nextpnr")
parser.add_argument("--cpu",
action="store_true",
help="Add a CPU to the build")
parser.add_argument(
"--debug",
action="store_true",
help="Add debug features. UART has to be used with the wishbone-tool.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
kwargs = builder_argdict(args)
print(kwargs)
if args.cpu:
kwargs["cpu_type"] = "vexriscv"
kwargs["cpu_variant"] = "min"
soc = BaseSoC(pnr_placer=args.placer,
pnr_seed=args.seed,
debug=args.debug,
**kwargs)
kwargs = builder_argdict(args)
# Don't build software -- we don't include it since we just jump
# to SPI flash.
kwargs["compile_software"] = False
builder = Builder(soc, **kwargs)
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
cls = BaseSoC
soc = cls(**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
def create_builder(soc, args):
builder = Builder(soc, **builder_argdict(args))
# builder.output_dir = args.output_dir
# required_packages = {"libcompiler_rt", "libbase"}
# # Select required packages. Of most importance is to exclude the "bios"
# # package, which is LiteX's BIOS, since we're using our own.
# builder.software_packages = [
# (name, dir) for (name, dir) in builder.software_packages if name in required_packages]
# # "bios" gets loaded automatically by the builder.
# builder.add_software_package("bios", f"{SOC_DIR}/software/bios")
return builder
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
cls = MinSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA_BX")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--seed", default=0, help="Seed to use in Nextpnr")
parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="Which placer to use in Nextpnr")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(pnr_placer=args.placer, pnr_seed=args.seed, debug=True, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
def main():
parser = argparse.ArgumentParser(description="Datapipe simulation SoC*")
builder_args(parser)
soc_core_args(parser)
# soc_core_args(parser)
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--ethernet-phy",
default="rgmii",
help="select Ethernet PHY (rgmii or 1000basex)")
parser.add_argument("-p",
"--program-only",
action="store_true",
help="Don't build, just program the existing bitfile")
parser.add_argument("--build",
action="store_true",
help="Build FPGA bitstream")
parser.add_argument("--load", action="store_true", help="program FPGA")
parser.add_argument("--threads",
default=4,
help="set number of threads (default=4)")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
soc_kwargs["integrated_main_ram_size"] = 0x10000
soc_kwargs = soc_core_argdict(args)
soc_kwargs["uart_name"] = "sim"
# sim_config.add_module("serial2console", "serial")
sim_config.add_module('ethernet',
"eth",
args={
"interface": "xxx1",
"ip": "192.168.88.101",
"vcd_name": "foo.vcd"
})
soc = SDRAMSimSoC(phy="rgmii",
with_ethernet=True,
with_etherbone=True,
with_sdram=True,
etherbone_ip_address="192.168.88.50",
etherbone_mac_address=0x12345678abcd,
**soc_kwargs)
builder = Builder(soc, **builder_argdict(args))
# discard result, or save in vns?
builder.build(threads=args.threads,
trace=args.trace,
sim_config=sim_config)
def build_soc(self, soc: litex_soc.LiteXSoC, **kwargs) -> builder.Builder:
"""Creates a LiteX Builder and builds the Soc if self.args.build.
Args:
soc: The LiteXSoC meant to be built.
**kwargs: Arguments meant to extend/overwrite the general
arguments to the LiteX Builder.
Returns:
The LiteX Builder for the SoC.
"""
copy_cpu_variant_if_needed(self.args.cpu_variant)
soc_builder = self.builder_constructor(
soc, **builder.builder_argdict(self.args))
soc_builder.build(run=self.args.build, **kwargs)
return soc_builder
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--flash-offset",
default=0x40000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=21e6,
help="Select system clock frequency")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../litex-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX RISC-V Example SOC",
author="Piotr Esden-Tempski")
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main():
parser = argparse.ArgumentParser(
description=__doc__, formatter_class=argparse.RawTextHelpFormatter)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq",
default=125e6,
help="System clock frequency (default: 125MHz)")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--with-rts-reset",
action="store_true",
help="Connect UART RTS line to sys_clk reset")
parser.add_argument("--with-bist",
action="store_true",
help="Add DDR3 BIST Generator/Checker")
parser.add_argument(
"--spd-dump",
type=str,
help=
"DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS"
)
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_bist=args.with_bist,
spd_dump=args.spd_dump,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
soc_cls = BaseSoC
cpu = VexRiscv
parser = argparse.ArgumentParser(description="LiteX SoC")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--build_gateware", action='store_true')
parser.add_argument("--yosys", action="store_true")
parser.add_argument("--sim", action="store_true")
parser.add_argument("--run", action="store_true")
args = parser.parse_args()
builder_kwargs = builder_argdict(args)
soc_kwargs = soc_core_argdict(args)
platform = sim_platform2.Platform() if args.sim else platform1.Platform()
output_dir = builder_kwargs['output_dir'] = 'build'
fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin")
soc_kwargs['integrated_rom_size'] = 32 * 1024
soc_kwargs["integrated_main_ram_size"] = 16 * 1024
try:
soc_kwargs['integrated_main_ram_init'] = get_mem_data(
fw_file, cpu.endianness)
except OSError:
pass
soc = BaseSoC(platform,
cpu=cpu,
sim=args.sim,
output_dir=output_dir,
**soc_kwargs)
builder = Builder(soc, **builder_kwargs)
builder.add_software_package("firmware",
src_dir=os.path.join(os.getcwd(), 'src',
'firmware'))
if args.sim:
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
builder.build(run=False, sim_config=sim_config, opt_level='O3')
if args.run:
builder.build(build=False, sim_config=sim_config)
else:
builder.build(run=args.build_gateware,
synth_mode="yosys" if args.yosys else "vivado")
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on the Arrow/Terasic SoCKit")
parser.add_argument(
"--single-rate-sdram",
action="store_true",
help="clock SDRAM with 1x the sytem clock (instead of 2x)")
parser.add_argument(
"--mister-sdram-xs-v22",
action="store_true",
help=
"Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card")
parser.add_argument(
"--mister-sdram-xs-v24",
action="store_true",
help=
"Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision",
default="revd",
help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
revision=args.revision,
sdram_rate="1:1" if args.single_rate_sdram else "1:2",
mister_sdram="xs_v22" if args.mister_sdram_xs_v22 else
"xs_v24" if args.mister_sdram_xs_v24 else None,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
import argparse
parser = argparse.ArgumentParser(description="10GbE test setup on KC705")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
print(args)
if args.build:
soc = DevSoC(sys_clk_freq=int(125e6), with_ethernet=args.with_ethernet, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(run=args.build)
# soc.analyzer.do_exit(vns)
if args.load:
prog = Platform().create_programmer()
prog.load_bitstream('build/xilinx_kc705/gateware/xilinx_kc705.bit')
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument(
"--board", choices=["evt", "pvt", "hacker"], required=True,
help="build for a particular hardware board"
)
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
)
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed,
debug=True, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
def main():
parser = argparse.ArgumentParser(description=__doc__)
builder_args(parser)
MySoc.basesoc_args(parser)
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
parser.add_argument("--rom-init", default=None,
help="rom_init file")
parser.set_defaults(
integrated_rom_size=0x8000,
integrated_main_ram_size=0x8000,
# integrated_sram_size=0, # Litex will complain if 0!
cpu_type="vexriscv",
platform="cmod_a7_sim",
clk_freq=int(1e6),
with_uart=False # We will add our own mock uart
)
args = parser.parse_args()
soc_kwargs = vars(args)
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
soc = MySoc(crg=CRG, **soc_kwargs)
# Push in a fake uart
soc.submodules.uart_phy = uart.RS232PHYModel(soc.platform.request("serial"))
soc.submodules.uart = uart.UART(soc.uart_phy)
sim_config = SimConfig(default_clk="sys_clk")
# sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
sim_config.add_module("serial2console", "serial")
# sim_config.add_module("serial2tcp", "serial", args={"port": 55555})
# now you can do these 2 things to get a terminal
# telnet localhost 55555
# litex_term socket://localhost:55555
# soc.add_constant("TFTP_SERVER_PORT", int(tftp_port))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=False, sim_config=sim_config, trace=args.trace)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--nextpnr-seed",
default=0,
help="Select nextpnr pseudo random seed")
parser.add_argument("--nextpnr-placer",
default="heap",
choices=["sa", "heap"],
help="Select nextpnr placer algorithm")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(debug=args.debug, **soc_core_argdict(args))
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed,
nextpnr_placer=args.nextpnr_placer)
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
builder = Builder(soc, **builder_kwargs)
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SoCKit")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision",
default="revd",
help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq",
default=50e6,
help="System clock frequency (default: 50MHz)")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
revision=args.revision,
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser.add_argument_group(title="Builder"))
soc_sdram_args(parser.add_argument_group(title="SoC SDRAM"))
group = parser.add_argument_group(title="LPDDR4 simulation")
group.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
group.add_argument("--trace", action="store_true", help="Enable Tracing")
group.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
group.add_argument("--trace-start",
default=0,
help="Cycle to start tracing")
group.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
group.add_argument("--trace-reset",
default=0,
help="Initial traceing state")
group.add_argument("--sys-clk-freq",
default="50e6",
help="Core clock frequency")
group.add_argument("--auto-precharge",
action="store_true",
help="Use DRAM auto precharge")
group.add_argument("--no-refresh",
action="store_true",
help="Disable DRAM refresher")
group.add_argument("--log-level",
default="all=INFO",
help="Set simulation logging level")
group.add_argument("--disable-delay",
action="store_true",
help="Disable CPU delays")
group.add_argument("--gtkw-savefile",
action="store_true",
help="Generate GTKWave savefile")
group.add_argument("--no-masked-write",
action="store_true",
help="Use LPDDR4 WRITE instead of MASKED-WRITE")
group.add_argument("--no-run",
action="store_true",
help="Don't run the simulation, just generate files")
group.add_argument("--double-rate-phy",
action="store_true",
help="Use sim PHY with 2-stage serialization")
group.add_argument("--finish-after-memtest",
action="store_true",
help="Stop simulation after DRAM memory test")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig()
sys_clk_freq = int(float(args.sys_clk_freq))
clocks = get_clocks(sys_clk_freq)
clocks.add_io(_io)
clocks.add_clockers(sim_config)
# Configuration --------------------------------------------------------------------------------
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
args.with_sdram = True
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(clocks=clocks,
auto_precharge=args.auto_precharge,
with_refresh=not args.no_refresh,
trace_reset=int(args.trace_reset),
log_level=args.log_level,
disable_delay=args.disable_delay,
masked_write=not args.no_masked_write,
double_rate_phy=args.double_rate_phy,
finish_after_memtest=args.finish_after_memtest,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
build_kwargs = dict(sim_config=sim_config,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
vns = builder.build(run=False, **build_kwargs)
if args.gtkw_savefile:
generate_gtkw_savefile(builder, vns, trace_fst=args.trace_fst)
if not args.no_run:
builder.build(build=False, **build_kwargs)
def get_builder_kwargs(args, target_name):
builder_kwargs = builder_argdict(args)
builder_kwargs["output_dir"] = os.path.join('build', target_name)
return builder_kwargs
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--flash-offset",
default=0x100000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=50e6,
help="Select system clock frequency")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument("--board",
default="5a-75b",
help="Board type: 5a-75b (default) or 5a-75e")
parser.add_argument("--revision",
default="7.0",
type=str,
help="Board revision 7.0 (default), 6.0 or 6.1")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--eth-phy",
default=0,
type=int,
help="Ethernet PHY 0 or 1 (default=0)")
parser.add_argument("--use-internal-osc",
action="store_true",
help="Use internal oscillator")
parser.add_argument(
"--sdram-rate",
default="1:1",
help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash",
action="store_true",
help="Load bitstream to flash")
parser.add_argument("--load",
action="store_true",
help="Load bitstream to SRAM")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
# Create the SOC
soc = BaseSoC(board=args.board,
revision=args.revision,
debug=args.debug,
flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
eth_phy=args.eth_phy,
use_internal_osc=args.use_internal_osc,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../rust/litex-pac/clSOC.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../rust/litex-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build(**trellis_argdict(args), run=args.build)
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="Colorlight 5A-75x LiteX Riscv SOC",
author="DerFetzer")
modify_memory_x(builder_kwargs)
modify_svd(builder_kwargs)
# If requested load the resulting bitstream onto the 5A-75X
if args.flash or args.load:
prog = ECP5Programmer()
if args.load:
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.flash:
prog.flash(
0x00000000,
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def get_builder_kwargs(args, target_name):
builder_kwargs = builder_argdict(args)
builder_kwargs["output_dir"] = os.path.join('build', target_name)
if args.docs:
builder_kwargs["compile_software"] = False
return builder_kwargs
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--flash-offset",
default=0x40000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=21e6,
help="Select system clock frequency")
parser.add_argument("--nextpnr-seed",
default=0,
help="Select nextpnr pseudo random seed")
parser.add_argument("--nextpnr-placer",
default="heap",
choices=["sa", "heap"],
help="Select nextpnr placer algorithm")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(debug=args.debug,
flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed,
nextpnr_placer=args.nextpnr_placer)
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../rust/icebesoc-pac/iCEBESOC.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../rust/icebesoc-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000,
"soc_basesoc_icebreaker/gateware/top.bin")
