def _generate_includes(self, with_bios=True): # Generate Include/Generated directories. _create_dir(self.include_dir) _create_dir(self.generated_dir) # Generate BIOS files when the SoC uses it. if with_bios: # Generate Variables to variables.mak. variables_contents = self._get_variables_contents() write_to_file(os.path.join(self.generated_dir, "variables.mak"), variables_contents) # Generate Output Format to output_format.ld. output_format_contents = export.get_linker_output_format(self.soc.cpu) write_to_file(os.path.join(self.generated_dir, "output_format.ld"), output_format_contents) # Generate Memory Regions to regions.ld. regions_contents = export.get_linker_regions(self.soc.mem_regions) write_to_file(os.path.join(self.generated_dir, "regions.ld"), regions_contents) # Collect / Generate I2C config and init table. from litex.soc.cores.bitbang import collect_i2c_info i2c_devs, i2c_init = collect_i2c_info(self.soc) if i2c_devs: i2c_info = export.get_i2c_header((i2c_devs, i2c_init)) write_to_file(os.path.join(self.generated_dir, "i2c.h"), i2c_info) # Generate Memory Regions to mem.h. mem_contents = export.get_mem_header(self.soc.mem_regions) write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents) # Generate Memory Regions to memory.x if specified. if self.memory_x is not None: memory_x_contents = export.get_memory_x(self.soc) write_to_file(os.path.realpath(self.memory_x), memory_x_contents) # Generate SoC Config/Constants to soc.h. soc_contents = export.get_soc_header(self.soc.constants) write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents) # Generate CSR registers definitions/access functions to csr.h. csr_contents = export.get_csr_header( regions = self.soc.csr_regions, constants = self.soc.constants, csr_base = self.soc.mem_regions['csr'].origin) write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents) # Generate Git SHA1 of tools to git.h git_contents = export.get_git_header() write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents) # Generate LiteDRAM C header to sdram_phy.h when the SoC use it if hasattr(self.soc, "sdram"): from litedram.init import get_sdram_phy_c_header sdram_contents = get_sdram_phy_c_header( self.soc.sdram.controller.settings.phy, self.soc.sdram.controller.settings.timing) write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"), sdram_contents)
def _generate_includes(self): # Generate Include/Generated directories. _create_dir(self.include_dir) _create_dir(self.generated_dir) # Generate BIOS files when the SoC uses it. with_bios = self.soc.cpu_type not in [None, "zynq7000"] if with_bios: # Generate Variables to variables.mak. variables_contents = [] def define(k, v): variables_contents.append("{}={}".format( k, _makefile_escape(v))) # Define the CPU variables. for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software): define(k, v) # Define the SoC/Compiler-RT/Software/Include directories. define("SOC_DIRECTORY", soc_directory) compiler_rt_directory = get_data_mod("software", "compiler_rt").data_location define("COMPILER_RT_DIRECTORY", compiler_rt_directory) variables_contents.append("export BUILDINC_DIRECTORY") define("BUILDINC_DIRECTORY", self.include_dir) for name, src_dir in self.software_packages: define(name.upper() + "_DIRECTORY", src_dir) # Define the BIOS Options. for bios_option in self.bios_options: assert bios_option in [ "TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE" ] define(bios_option, "1") # Write to variables.mak. write_to_file(os.path.join(self.generated_dir, "variables.mak"), "\n".join(variables_contents)) # Generate Output Format to output_format.ld. output_format_contents = export.get_linker_output_format( self.soc.cpu) write_to_file(os.path.join(self.generated_dir, "output_format.ld"), output_format_contents) # Generate Memory Regions to regions.ld. regions_contents = export.get_linker_regions(self.soc.mem_regions) write_to_file(os.path.join(self.generated_dir, "regions.ld"), regions_contents) # Generate Memory Regions to mem.h. mem_contents = export.get_mem_header(self.soc.mem_regions) write_to_file(os.path.join(self.generated_dir, "mem.h"), mem_contents) # Generate Memory Regions to memory.x if specified. if self.memory_x is not None: memory_x_contents = export.get_memory_x(self.soc) write_to_file(os.path.realpath(self.memory_x), memory_x_contents) # Generate SoC Config/Constants to soc.h. soc_contents = export.get_soc_header(self.soc.constants) write_to_file(os.path.join(self.generated_dir, "soc.h"), soc_contents) # Generate CSR registers definitions/access functions to csr.h. csr_contents = export.get_csr_header( regions=self.soc.csr_regions, constants=self.soc.constants, csr_base=self.soc.mem_regions['csr'].origin) write_to_file(os.path.join(self.generated_dir, "csr.h"), csr_contents) # Generate Git SHA1 of tools to git.h git_contents = export.get_git_header() write_to_file(os.path.join(self.generated_dir, "git.h"), git_contents) # Generate LiteDRAM C header to sdram_phy.h when the SoC use it. if hasattr(self.soc, "sdram"): from litedram.init import get_sdram_phy_c_header sdram_contents = get_sdram_phy_c_header( self.soc.sdram.controller.settings.phy, self.soc.sdram.controller.settings.timing) write_to_file(os.path.join(self.generated_dir, "sdram_phy.h"), sdram_contents)
def _generate_mem_region_map(self): if self.memory_x is not None: memory_x_dir = os.path.dirname(os.path.realpath(self.memory_x)) os.makedirs(memory_x_dir, exist_ok=True) write_to_file(self.memory_x, export.get_memory_x(self.soc))