def __init__(self, platform):
sys_clk_freq = int(125e6)
SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32,
ident="LitePCIe example design", ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform)
# PCIe PHY ---------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"))
self.add_csr("pcie_phy")
# PCIe Endpoint ----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# PCIe Wishbone bridge ---------------------------------------------------------------------
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)
self.add_wb_master(self.pcie_bridge.wishbone)
# PCIe DMA ---------------------------------------------------------------------------------
self.submodules.pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
self.add_csr("pcie_dma")
# PCIe MSI ---------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA_WRITER": self.pcie_dma.writer.irq,
"PCIE_DMA_READER": self.pcie_dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
def __init__(self, platform, core_config):
# # PHY --------------------------------------------------------------------------------------
# PHYCore.__init__(self, platform, core_config)
# SoC parameters ---------------------------------------------------------------------------
soc_args = {}
if "soc" in core_config:
soc_config = core_config["soc"]
for arg in soc_config:
if arg in ("csr_map", "interrupt_map", "mem_map"):
getattr(self, arg).update(soc_config[arg])
else:
soc_args[arg] = soc_config[arg]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=core_config["clk_freq"],
**soc_args)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset"))
# PHY ----------------------------------------------------------------------------------
ethphy = LiteEthPHYModel(pads=platform.request("model_eth"))
self.submodules.ethphy = ethphy
self.add_csr("ethphy")
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt_request").eq(
self.ethmac.ev.irq)
def __init__(self, platform, **kwargs):
self.clock_domains.cd_sys = ClockDomain()
clk = platform.request("clk")
platform.add_period_constraint(clk, 1e9 / 12e6)
# This allows PLLs/MMCMEs to be placed anywhere and reference the input clock
self.specials += Instance("BUFG", i_I=clk, o_O=self.cd_sys.clk)
SoCMini.__init__(self, platform, clk_freq=12e6, **kwargs)
# ROM test ---------------------------------------------------------------------------------
self.submodules.romtest = RomTest(platform,
platform.request("address"),
platform.request("data"))
def __init__(self, platform, **kwargs):
self.sys_clk_freq = int(100e6)
SoCMini.__init__(self, platform, self.sys_clk_freq, csr_data_width=32,
ident="My first LiteX System On Chip", ident_version=True)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("user_btn", 0))
serial = platform.request("serial", 0)
self.submodules.serial_bridge = UARTWishboneBridge(serial, self.sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
self.add_uart("uart0", 115200)
self.add_uart("uart1", 115200)
self.add_uart("uart2", 230400)
self.add_uart("uart3", 230400)
self.add_constant("UART_POLLING")
def __init__(self, platform, clk_freq=100 * 1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCMini.__init__(
self,
platform,
clk_freq,
csr_data_width=32,
with_uart=True,
uart_name="bridge",
ident="Litescope example design",
ident_version=True,
)
self.submodules.analyzer = LiteScopeAnalyzer(platform.request("bus"),
512)
self.add_csr("analyzer")
def __init__(self, platform):
sys_clk_freq = int((1e9 / platform.default_clk_period))
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(
self,
platform,
sys_clk_freq,
csr_data_width=32,
with_uart=True,
uart_name="bridge",
ident="Litescope example design",
ident_version=True,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Litescope IO -----------------------------------------------------------------------------
self.submodules.io = LiteScopeIO(8)
self.add_csr("io")
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer -----------------------------------------------------------------------
analyzer_groups = {}
# Counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [
zero,
counter,
]
# Communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx,
self.bus.masters["uartbone"],
]
# FSM group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1", NextState("STATE2"))
fsm.act("STATE2", NextState("STATE1"))
analyzer_groups[2] = [
fsm,
]
# Analyzer
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_groups, 512, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")