def __init__(self, init):
init = init + [0x00] * (self.size - len(init))
self.mem = Memory(8, self.size, init=init, name='mem_main_ram')
self.ibus = csr_bus.Interface(data_width=32, address_width=16, alignment=8)
self.dbus = self.bus = _data_bus()
self.add_ibus_port()
self.add_dbus_port()
def add_csr_bridge(self, origin):
self.submodules.csr_bridge = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=self.csr.address_width,
data_width=self.csr.data_width))
csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region)
self.csr.add_master(name="bridge", master=self.csr_bridge.csr)
self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def __init__(self):
self.csr = csr_bus.Interface(data_width=32, address_width=12)
self.axi = axi_lite.Interface(data_width=32, address_width=14)
self.submodules.csrmodule = CSRModule()
self.submodules.dut = axi_lite.AXILite2CSR(self.axi, self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
self.map_csr,
data_width=32,
address_width=12)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
def __init__(self, bus_wishbone=None, bus_csr=None, register=True):
self.csr = bus_csr
if self.csr is None:
# If no CSR bus provided, create it with default parameters.
self.csr = csr_bus.Interface()
self.wishbone = bus_wishbone
if self.wishbone is None:
# If no Wishbone bus provided, create it with default parameters.
self.wishbone = Interface()
# # #
if register:
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
NextValue(self.csr.dat_w, self.wishbone.dat_w),
If(self.wishbone.cyc & self.wishbone.stb,
NextValue(self.csr.adr, self.wishbone.adr),
NextValue(self.csr.we, self.wishbone.we & (self.wishbone.sel != 0)),
NextState("WRITE-READ")
)
)
fsm.act("WRITE-READ",
NextValue(self.csr.adr, 0),
NextValue(self.csr.we, 0),
NextState("ACK")
)
fsm.act("ACK",
self.wishbone.ack.eq(1),
self.wishbone.dat_r.eq(self.csr.dat_r),
NextState("IDLE")
)
else:
fsm = FSM(reset_state="WRITE-READ")
self.submodules += fsm
fsm.act("WRITE-READ",
self.csr.dat_w.eq(self.wishbone.dat_w),
If(self.wishbone.cyc & self.wishbone.stb,
self.csr.adr.eq(self.wishbone.adr),
self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
NextState("ACK")
)
)
fsm.act("ACK",
self.wishbone.ack.eq(1),
self.wishbone.dat_r.eq(self.csr.dat_r),
NextState("WRITE-READ")
)
def __init__(self, axi_lite=None, bus_csr=None):
if axi_lite is None:
axi_lite = AXILiteInterface()
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.axi_lite = axi_lite
self.csr = bus_csr
fsm, comb = axi_lite_to_simple(axi_lite=self.axi_lite,
port_adr=self.csr.adr,
port_dat_r=self.csr.dat_r,
port_dat_w=self.csr.dat_w,
port_we=self.csr.we)
self.submodules.fsm = fsm
self.comb += comb
def __init__(self, platform, ea=Constant(0)):
self.platform = platform
self.interrupt = Signal(2)
self.ibus = i = csr_bus.Interface(data_width=32,
address_width=16,
alignment=8)
self.dbus = d = wishbone.Interface(data_width=8, adr_width=16)
# connect to the verilog 8051 core
cpu_connections = dict(
# clock and reset
i_wb_rst_i=ResetSignal(),
i_wb_clk_i=ClockSignal(),
# 2 interrupt pins
i_int0_i=self.interrupt[0],
i_int1_i=self.interrupt[1],
# external access, EA=1 means that internal ROM is also used
i_ea_in=ea,
# ROM interface, we do not use wishbone so some signals are not used
o_wbi_adr_o=i.adr,
i_wbi_dat_i=i.dat_r, # slave to master
i_wbi_ack_i=Constant(1), # data is always valid
# i_wbi_err_i = Signal(),
# o_wbi_stb_o = Signal(),
# o_wbi_cyc_o = Signal(),
# external data RAM interface
o_wbd_adr_o=d.adr,
o_wbd_dat_o=d.dat_w,
i_wbd_dat_i=d.dat_r,
o_wbd_we_o=d.we,
i_wbd_ack_i=d.ack,
i_wbd_err_i=d.err,
o_wbd_stb_o=d.stb,
o_wbd_cyc_o=d.cyc,
)
self.specials += Instance("oc8051_top", **cpu_connections)
vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)),
"verilog")
platform.add_sources(os.path.join(vdir, "rtl", "8051", "oc8051_top.v"))
platform.add_verilog_include_path(os.path.join(vdir, "rtl", "8051"))
platform.add_verilog_include_path(os.path.join(vdir, "rtl", "defs"))
def __init__(self, bus_wishbone=None, bus_csr=None):
if bus_wishbone is None:
bus_wishbone = wishbone.Interface()
self.wishbone = bus_wishbone
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.csr = bus_csr
###
self.sync += [
self.csr.we.eq(0),
self.csr.dat_w.eq(self.wishbone.dat_w),
self.csr.adr.eq(self.wishbone.adr),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
self.sync += timeline(self.wishbone.cyc & self.wishbone.stb,
[(1, [self.csr.we.eq(self.wishbone.we)]),
(2, [self.wishbone.ack.eq(1)]),
(3, [self.wishbone.ack.eq(0)])])
def __init__(self, bus_wishbone=None, bus_csr=None):
if bus_wishbone is None:
bus_wishbone = wishbone.Interface()
self.wishbone = bus_wishbone
if bus_csr is None:
bus_csr = csr_bus.Interface()
self.csr = bus_csr
# # #
self.comb += [
self.csr.dat_w.eq(self.wishbone.dat_w),
self.wishbone.dat_r.eq(self.csr.dat_r)
]
fsm = FSM(reset_state="WRITE-READ")
self.submodules += fsm
fsm.act(
"WRITE-READ",
If(self.wishbone.cyc & self.wishbone.stb,
self.csr.adr.eq(self.wishbone.adr),
self.csr.we.eq(self.wishbone.we), NextState("ACK")))
fsm.act("ACK", self.wishbone.ack.eq(1), NextState("WRITE-READ"))
def __init__(
self,
platform,
clk_freq,
# CPU parameters
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
# ROM parameters
integrated_rom_size=0,
integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096,
integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0,
integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8,
csr_alignment=32,
csr_address_width=14,
# Identifier parameters
ident="",
ident_version=False,
# UART parameters
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True,
wishbone_timeout_cycles=1e6,
**kwargs):
self.platform = platform
self.clk_freq = clk_freq
# SoC's CSR/Mem/Interrupt mapping (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
self.soc_io_regions = self.io_regions
# SoC's Config/Constants/Regions
self.config = {}
self.constants = {}
self.mem_regions = {}
self.csr_regions = {}
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
self.add_retro_compat(kwargs)
# Parameters managment ---------------------------------------------------------------------
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(
cpu_variant.split('+')[0]).upper()
# Check type
if cpu_type not in cpu.CPUS.keys():
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add the CPU
self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant))
# Update Memory Map (if defined by CPU)
self.soc_mem_map.update(self.cpu.mem_map)
# Update IO Regions (if defined by CPU)
self.soc_io_regions.update(self.cpu.io_regions)
# Set reset address
self.cpu.set_reset_address(
self.soc_mem_map["rom"]
if integrated_rom_size else cpu_reset_address)
self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
# Add CPU buses as 32-bit Wishbone masters
for cpu_bus in self.cpu.buses:
assert cpu_bus.data_width in [32, 64, 128]
soc_bus = wishbone.Interface(data_width=32)
self.submodules += wishbone.Converter(cpu_bus, soc_bus)
self.add_wb_master(soc_bus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU interrupts
for _name, _id in self.cpu.interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
else:
self.add_cpu(cpu.CPUNone())
self.soc_io_regions.update(self.cpu.io_regions)
# Add user's interrupts (needs to be done after CPU interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + get_version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
csr_alignment = max(csr_alignment, self.cpu.data_width)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(address_width=csr_address_width,
data_width=csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone, 0x1000000)
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_baudrate=115200,
ident="",
with_timer=True):
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if with_uart:
self.submodules.uart_phy = uart.RS232PHY(
platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
if ident:
self.submodules.identifier = identifier.Identifier(ident)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
def __init__(self,
platform,
clk_freq,
cpu_type="lm32",
cpu_reset_address=0x00000000,
cpu_variant=None,
integrated_rom_size=0,
integrated_rom_init=[],
integrated_sram_size=4096,
integrated_main_ram_size=0,
integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
ident="",
ident_version=False,
reserve_nmi_interrupt=True,
with_timer=True):
self.config = dict()
self.platform = platform
self.clk_freq = clk_freq
self.cpu_type = cpu_type
self.cpu_variant = cpu_variant
if integrated_rom_size:
cpu_reset_address = self.mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu_or_bridge(
lm32.LM32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "or1k":
self.add_cpu_or_bridge(
mor1kx.MOR1KX(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "riscv32":
self.add_cpu_or_bridge(
picorv32.PicoRV32(platform, self.cpu_reset_address,
self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)
self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.mem_map["csr"],
self.wishbone2csr.wishbone)
if reserve_nmi_interrupt:
self.soc_interrupt_map[
"nmi"] = 0 # Reserve zero for "non-maskable interrupt"
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
#else:
# del self.soc_interrupt_map["uart"]
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
else:
del self.soc_interrupt_map["timer0"]
# Invert the interrupt map.
interrupt_rmap = {}
for mod_name, interrupt in self.interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with user defined %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
interrupt_rmap[interrupt] = mod_name
# Add the base SoC's interrupt map
for mod_name, interrupt in self.soc_interrupt_map.items():
assert interrupt not in interrupt_rmap, (
"Interrupt vector conflict for IRQ %s, user defined %s conflicts with SoC inbuilt %s"
% (interrupt, mod_name, interrupt_rmap[interrupt]))
self.interrupt_map[mod_name] = interrupt
interrupt_rmap[interrupt] = mod_name
# Make sure other functions are not using this value.
self.soc_interrupt_map = None
# Make the interrupt vector read only
self.interrupt_map = ReadOnlyDict(self.interrupt_map)
# Save the interrupt reverse map
self.interrupt_rmap = ReadOnlyDict(interrupt_rmap)
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# FIXME: RocketChip reserves the first 256Mbytes for internal use
# remap rom to 0x10000000, sram to 0x20000000
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x20000000
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
# Support the old style which used underscore for separator
if cpu_variant is None:
cpu_variant = "standard"
cpu_variant = cpu_variant.replace('_', '+')
# Check for valid CPU variants.
cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
for key, values in CPU_VARIANTS.items():
if cpu_variant_processor not in [key,]+values:
continue
self.cpu_variant = key
break
else:
raise InvalidCPUVariantError(cpu_variant)
# Check for valid CPU extensions.
for ext in sorted(cpu_variant_ext):
if ext not in CPU_VARIANTS_EXTENSIONS:
raise InvalidCPUExtensionError(cpu_variant)
self.cpu_variant += "+"+ext
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add Wishbone to CSR bridge
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
# Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"]
csr_expose = core_config.get("csr_expose", False)
csr_align = core_config.get("csr_align", 32)
if cpu_type is None:
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0
kwargs["min_l2_data_width"] = 0
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = False
else:
kwargs["l2_size"] = 0
kwargs["min_l2_data_width"] = 0
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(
self,
platform,
sys_clk_freq,
cpu_type=cpu_type,
csr_alignment=csr_align,
max_sdram_size=
0x01000000, # Only expose 16MB to the CPU, enough for Init/Calib.
**kwargs)
# CRG --------------------------------------------------------------------------------------
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(
platform, core_config)
if core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
# DRAM -------------------------------------------------------------------------------------
platform.add_extension(get_dram_ios(core_config))
if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
assert core_config["memtype"] in ["DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"), sys_clk_freq=sys_clk_freq)
self.comb += crg.stop.eq(self.ddrphy.init.stop)
sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
if core_config["sdram_phy"] in [
litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY,
litedram_phys.V7DDRPHY
]:
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
pads=platform.request("ddram"),
memtype=core_config["memtype"],
nphases=4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=core_config["iodelay_clk_freq"],
cmd_latency=core_config["cmd_latency"])
self.add_constant("CMD_DELAY", core_config["cmd_delay"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
self.add_csr("ddrphy")
sdram_module = core_config["sdram_module"](
sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2")
controller_settings = controller_settings = ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings,
controller_settings=controller_settings)
# DRAM Initialization ----------------------------------------------------------------------
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
self.comb += [
platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage)
]
# CSR port ---------------------------------------------------------------------------------
if csr_expose:
csr_port = csr_bus.Interface(address_width=self.csr_address_width,
data_width=self.csr_data_width)
self.add_csr_master(csr_port)
platform.add_extension(
get_csr_ios(self.csr_address_width, self.csr_data_width))
_csr_port_io = platform.request("csr_port", 0)
self.comb += [
csr_port.adr.eq(_csr_port_io.adr),
csr_port.we.eq(_csr_port_io.we),
csr_port.dat_w.eq(_csr_port_io.dat_w),
_csr_port_io.dat_r.eq(csr_port.dat_r),
]
if self.cpu_type == None:
csr_base = core_config.get("csr_base", 0)
self.shadow_base = csr_base
# User ports -------------------------------------------------------------------------------
self.comb += [
platform.request("user_clk").eq(ClockSignal()),
platform.request("user_rst").eq(ResetSignal())
]
for name, port in core_config["user_ports"].items():
# Native -------------------------------------------------------------------------------
if port["type"] == "native":
user_port = self.sdram.crossbar.get_port()
platform.add_extension(
get_native_user_port_ios(name, user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# cmd
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),
_user_port_io.wdata_ready.eq(user_port.wdata.ready),
user_port.wdata.we.eq(_user_port_io.wdata_we),
user_port.wdata.data.eq(_user_port_io.wdata_data),
# rdata
_user_port_io.rdata_valid.eq(user_port.rdata.valid),
user_port.rdata.ready.eq(_user_port_io.rdata_ready),
_user_port_io.rdata_data.eq(user_port.rdata.data),
]
# Wishbone -----------------------------------------------------------------------------
elif port["type"] == "wishbone":
user_port = self.sdram.crossbar.get_port()
wb_port = wishbone.Interface(user_port.data_width,
user_port.address_width)
wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
self.submodules += wishbone2native
platform.add_extension(
get_wishbone_user_port_ios(name, len(wb_port.adr),
len(wb_port.dat_w)))
_wb_port_io = platform.request("user_port_{}".format(name))
self.comb += [
wb_port.adr.eq(_wb_port_io.adr),
wb_port.dat_w.eq(_wb_port_io.dat_w),
_wb_port_io.dat_r.eq(wb_port.dat_r),
wb_port.sel.eq(_wb_port_io.sel),
wb_port.cyc.eq(_wb_port_io.cyc),
wb_port.stb.eq(_wb_port_io.stb),
_wb_port_io.ack.eq(wb_port.ack),
wb_port.we.eq(_wb_port_io.we),
_wb_port_io.err.eq(wb_port.err),
]
# AXI ----------------------------------------------------------------------------------
elif port["type"] == "axi":
user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(
user_port.data_width, user_port.address_width +
log2_int(user_port.data_width // 8), port["id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native
platform.add_extension(
get_axi_user_port_ios(name, axi_port.address_width,
axi_port.data_width,
port["id_width"]))
_axi_port_io = platform.request("user_port_{}".format(name))
self.comb += [
# aw
axi_port.aw.valid.eq(_axi_port_io.awvalid),
_axi_port_io.awready.eq(axi_port.aw.ready),
axi_port.aw.addr.eq(_axi_port_io.awaddr),
axi_port.aw.burst.eq(_axi_port_io.awburst),
axi_port.aw.len.eq(_axi_port_io.awlen),
axi_port.aw.size.eq(_axi_port_io.awsize),
axi_port.aw.id.eq(_axi_port_io.awid),
# w
axi_port.w.valid.eq(_axi_port_io.wvalid),
_axi_port_io.wready.eq(axi_port.w.ready),
axi_port.w.last.eq(_axi_port_io.wlast),
axi_port.w.strb.eq(_axi_port_io.wstrb),
axi_port.w.data.eq(_axi_port_io.wdata),
# b
_axi_port_io.bvalid.eq(axi_port.b.valid),
axi_port.b.ready.eq(_axi_port_io.bready),
_axi_port_io.bresp.eq(axi_port.b.resp),
_axi_port_io.bid.eq(axi_port.b.id),
# ar
axi_port.ar.valid.eq(_axi_port_io.arvalid),
_axi_port_io.arready.eq(axi_port.ar.ready),
axi_port.ar.addr.eq(_axi_port_io.araddr),
axi_port.ar.burst.eq(_axi_port_io.arburst),
axi_port.ar.len.eq(_axi_port_io.arlen),
axi_port.ar.size.eq(_axi_port_io.arsize),
axi_port.ar.id.eq(_axi_port_io.arid),
# r
_axi_port_io.rvalid.eq(axi_port.r.valid),
axi_port.r.ready.eq(_axi_port_io.rready),
_axi_port_io.rlast.eq(axi_port.r.last),
_axi_port_io.rresp.eq(axi_port.r.resp),
_axi_port_io.rdata.eq(axi_port.r.data),
_axi_port_io.rid.eq(axi_port.r.id),
]
# FIFO ---------------------------------------------------------------------------------
elif port["type"] == "fifo":
platform.add_extension(
get_fifo_user_port_ios(name, user_port.data_width))
_user_fifo_io = platform.request("user_fifo_{}".format(name))
fifo = LiteDRAMFIFO(
data_width=user_port.data_width,
base=port["base"],
depth=port["depth"],
write_port=self.sdram.crossbar.get_port("write"),
write_threshold=port["depth"] - 32, # FIXME
read_port=self.sdram.crossbar.get_port("read"),
read_threshold=32 # FIXME
)
self.submodules += fifo
self.comb += [
# in
fifo.sink.valid.eq(_user_fifo_io.in_valid),
_user_fifo_io.in_ready.eq(fifo.sink.ready),
fifo.sink.data.eq(_user_fifo_io.in_data),
# out
_user_fifo_io.out_valid.eq(fifo.source.valid),
fifo.source.ready.eq(_user_fifo_io.out_ready),
_user_fifo_io.out_data.eq(fifo.source.data),
]
else:
raise ValueError("Unsupported port type: {}".format(
port["type"]))
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_alignment=32, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
with_wishbone=True, wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# NOTE: RocketChip reserves the first 256Mbytes for internal use,
# so we must change default mem_map;
# Also, CSRs *must* be 64-bit aligned.
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x11000000
self.soc_mem_map["csr"] = 0x12000000
csr_alignment = 64
# Mainline Linux OpenRISC arch code requires Linux kernel to be loaded
# at the physical address of 0x0. As we are running Linux from the
# MAIN_RAM region - move it to satisfy that requirement.
if cpu_type == "mor1kx" and cpu_variant == "linux":
self.soc_mem_map["main_ram"] = 0x00000000
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x50000000
self.soc_mem_map["csr"] = 0x60000000
if cpu_type == "None":
cpu_type = None
if not with_wishbone:
self.soc_mem_map["csr"] = 0x00000000
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert csr_alignment in [32, 64]
assert 2**(csr_address_width + 2) <= 0x1000000
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.with_wishbone = with_wishbone
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
elif uart_name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY
self.submodules.uart_phy = JTAGPHY(device=platform.device)
else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Add Wishbone to CSR bridge
self.config["CSR_DATA_WIDTH"] = self.csr_data_width
self.config["CSR_ALIGNMENT"] = self.csr_alignment
if with_wishbone:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(
address_width=self.csr_address_width,
data_width=self.csr_data_width))
self.add_csr_master(self.wishbone2csr.csr)
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
def __init__(self):
self.axi_lite = AXILiteInterface()
self.csr = csr_bus.Interface()
self.submodules.axilite2csr = AXILite2CSR(
self.axi_lite, self.csr)
self.errors = 0
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
sys_clk_freq = core_config["sys_clk_freq"]
SoCSDRAM.__init__(self,
platform,
sys_clk_freq,
cpu_type=core_config["cpu"],
l2_size=16 * core_config["sdram_module_nb"],
**kwargs)
# crg
self.submodules.crg = LiteDRAMCRG(platform, core_config)
# sdram
platform.add_extension(get_dram_ios(core_config))
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
platform.request("ddram"),
memtype=core_config["memtype"],
nphases=4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=core_config["iodelay_clk_freq"],
cmd_latency=core_config["cmd_latency"])
self.add_constant("CMD_DELAY", core_config["cmd_delay"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
sdram_module = core_config["sdram_module"](
sys_clk_freq, "1:4" if core_config["memtype"] == "DDR3" else "1:2")
controller_settings = controller_settings = ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
# sdram init
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.comb += [
platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage)
]
# CSR port
if core_config.get("expose_csr_port", "no") == "yes":
csr_port = csr_bus.Interface(self.csr_address_width,
self.csr_data_width)
self.add_csr_master(csr_port)
platform.add_extension(
get_csr_ios(self.csr_address_width, self.csr_data_width))
_csr_port_io = platform.request("csr_port", 0)
self.comb += [
csr_port.adr.eq(_csr_port_io.adr),
csr_port.we.eq(_csr_port_io.we),
csr_port.dat_w.eq(_csr_port_io.dat_w),
_csr_port_io.dat_r.eq(csr_port.dat_r),
]
# user port
self.comb += [
platform.request("user_clk").eq(ClockSignal()),
platform.request("user_rst").eq(ResetSignal())
]
if core_config["user_ports_type"] == "native":
for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port()
platform.add_extension(
get_native_user_port_ios(i, user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port", i)
self.comb += [
# cmd
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),
_user_port_io.wdata_ready.eq(user_port.wdata.ready),
user_port.wdata.we.eq(_user_port_io.wdata_we),
user_port.wdata.data.eq(_user_port_io.wdata_data),
# rdata
_user_port_io.rdata_valid.eq(user_port.rdata.valid),
user_port.rdata.ready.eq(_user_port_io.rdata_ready),
_user_port_io.rdata_data.eq(user_port.rdata.data),
]
elif core_config["user_ports_type"] == "axi":
for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(
user_port.data_width, user_port.address_width +
log2_int(user_port.data_width // 8),
core_config["user_ports_id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native
platform.add_extension(
get_axi_user_port_ios(i, axi_port.address_width,
axi_port.data_width,
core_config["user_ports_id_width"]))
_axi_port_io = platform.request("user_port", i)
self.comb += [
# aw
axi_port.aw.valid.eq(_axi_port_io.aw_valid),
_axi_port_io.aw_ready.eq(axi_port.aw.ready),
axi_port.aw.addr.eq(_axi_port_io.aw_addr),
axi_port.aw.burst.eq(_axi_port_io.aw_burst),
axi_port.aw.len.eq(_axi_port_io.aw_len),
axi_port.aw.size.eq(_axi_port_io.aw_size),
axi_port.aw.id.eq(_axi_port_io.aw_id),
# w
axi_port.w.valid.eq(_axi_port_io.w_valid),
_axi_port_io.w_ready.eq(axi_port.w.ready),
axi_port.w.last.eq(_axi_port_io.w_last),
axi_port.w.strb.eq(_axi_port_io.w_strb),
axi_port.w.data.eq(_axi_port_io.w_data),
# b
_axi_port_io.b_valid.eq(axi_port.b.valid),
axi_port.b.ready.eq(_axi_port_io.b_ready),
_axi_port_io.b_resp.eq(axi_port.b.resp),
_axi_port_io.b_id.eq(axi_port.b.id),
# ar
axi_port.ar.valid.eq(_axi_port_io.ar_valid),
_axi_port_io.ar_ready.eq(axi_port.ar.ready),
axi_port.ar.addr.eq(_axi_port_io.ar_addr),
axi_port.ar.burst.eq(_axi_port_io.ar_burst),
axi_port.ar.len.eq(_axi_port_io.ar_len),
axi_port.ar.size.eq(_axi_port_io.ar_size),
axi_port.ar.id.eq(_axi_port_io.ar_id),
# r
_axi_port_io.r_valid.eq(axi_port.r.valid),
axi_port.r.ready.eq(_axi_port_io.r_ready),
_axi_port_io.r_last.eq(axi_port.r.last),
_axi_port_io.r_resp.eq(axi_port.r.resp),
_axi_port_io.r_data.eq(axi_port.r.data),
_axi_port_io.r_id.eq(axi_port.r.id),
]
else:
raise ValueError("Unsupported port type: {}".format(
core_config["user_ports_type"]))
def __init__(self):
# AXI is byte addressed, CSR is word addressed...
self.axi_width = 16
self.csr_width = self.axi_width - 2
self._csr_map = {}
self._csr_reverse_map = {}
self.submodules.offsetdac = OffsetDac()
self.offsetdac_mux = self.offsetdac.mux
self.offsetdac_spi = self.offsetdac.spi
self.adc0 = Signal(20) # DP1A, DN1A, ...DN4B, LCLK, FCLK each p/n
# AXIS ADC0 data
self.adc_axis_clk = Signal()
self.adc_axis_rst = Signal()
self.adc0_tdata = Signal(64)
self.adc0_tvalid = Signal()
self.adc0_tready = Signal()
self.debug = Signal(64)
self.lvds_pads_adc0 = Record(LVDS_ADC)
for i in range(8):
self.comb += [
self.lvds_pads_adc0.d_p[i].eq(self.adc0[i * 2 + 0]),
self.lvds_pads_adc0.d_n[i].eq(self.adc0[i * 2 + 1]),
]
self.comb += [
self.lvds_pads_adc0.lclk_p.eq(self.adc0[16]),
self.lvds_pads_adc0.lclk_n.eq(self.adc0[17]),
self.lvds_pads_adc0.fclk_p.eq(self.adc0[18]),
self.lvds_pads_adc0.fclk_n.eq(self.adc0[19]),
]
self.submodules.lvds_adc0 = LvdsReceiver(self.lvds_pads_adc0)
# wire up AXIS
self.comb += [
self.lvds_adc0.d_clk.eq(self.adc_axis_clk), # data clock
self.lvds_adc0.d_rst.eq(self.adc_axis_rst), # data reset
self.adc0_tdata.eq(self.lvds_adc0.d),
self.adc0_tvalid.eq(self.lvds_adc0.d_valid),
self.lvds_adc0.d_ready.eq(self.adc0_tready)
]
# DEBUG
count = Signal(20)
self.clock_domains.cd_data = ClockDomain()
self.comb += self.cd_data.clk.eq(self.adc_axis_clk)
self.comb += self.cd_data.rst.eq(self.adc_axis_rst)
self.sync.data += [count.eq(count + 1)]
self.comb += [
self.debug[0:32].eq(self.lvds_adc0.d),
self.debug[32:40].eq(self.lvds_adc0.fclk_preslip),
self.debug[40].eq(self.lvds_adc0.d_valid),
self.debug[41].eq(self.adc0_tvalid),
self.debug[42].eq(self.adc0_tready), self.debug[45:64].eq(count)
]
self.axi_lite = axi.Interface(data_width=32,
address_width=self.axi_width)
self.csr = csr_bus.Interface(data_width=32,
address_width=self.csr_width)
self.submodules.axi2csr = axi.AXILite2CSR(bus_axi=self.axi_lite,
bus_csr=self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self._get_csr_map,
data_width=32,
address_width=self.csr_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
self.ios = set()
for i in self.axi_lite, self.offsetdac_mux, self.offsetdac_spi:
self.ios |= set(i.flatten())
self.ios |= set([
self.debug, self.adc0, self.adc0_tdata, self.adc0_tvalid,
self.adc0_tready, self.adc_axis_clk, self.adc_axis_rst
])
def __init__(self, num_adcs=2):
# AXI is byte addressed, CSR is word addressed...
self.axi_width = 16
self.csr_width = self.axi_width - 2
self._csr_map = {}
self._csr_reverse_map = {}
self.submodules.offsetdac = OffsetDac()
self.offsetdac_mux = self.offsetdac.mux
self.offsetdac_spi = self.offsetdac.spi
# DEBUG
count = Signal(20)
self.sync.data += [count.eq(count + 1)]
self.debug = Signal(64)
# common across all ADC channels
self.adc_axis_clk = Signal()
self.adc_axis_rst = Signal()
def create_signal(name, signal):
setattr(self, name, signal)
getattr(self, name).name_override = name
return signal
# per-ADC signals
for nadc in range(num_adcs):
adc = create_signal("adc%d" % nadc, Signal(20))
adc_tdata = create_signal("adc%d_tdata" % nadc, Signal(64))
adc_tvalid = create_signal("adc%d_tvalid" % nadc, Signal())
adc_tready = create_signal("adc%d_tready" % nadc, Signal())
adc_tlast = create_signal("adc%d_tlast" % nadc, Signal())
lvds_pads_adc = Record(LVDS_ADC)
for i in range(8):
self.comb += [
lvds_pads_adc.d_p[i].eq(adc[i * 2 + 0]),
lvds_pads_adc.d_n[i].eq(adc[i * 2 + 1]),
]
self.comb += [
lvds_pads_adc.lclk_p.eq(adc[16]),
lvds_pads_adc.lclk_n.eq(adc[17]),
lvds_pads_adc.fclk_p.eq(adc[18]),
lvds_pads_adc.fclk_n.eq(adc[19]),
]
adcif = LvdsReceiver(lvds_pads_adc, nadc)
if nadc == 1:
self.comb += [
self.debug[0:32].eq(adcif.d),
self.debug[32:40].eq(adcif.fclk_preslip),
self.debug[40].eq(adcif.d_valid),
self.debug[41].eq(adcif.d_last),
self.debug[42].eq(adcif.d_ready),
self.debug[45:64].eq(count)
]
self.comb += [
adcif.d_clk.eq(self.adc_axis_clk), # data clock
adcif.d_rst.eq(self.adc_axis_rst), # data reset
adc_tdata.eq(adcif.d),
adc_tvalid.eq(adcif.d_valid),
adcif.d_ready.eq(adc_tready),
adc_tlast.eq(adcif.d_last),
]
setattr(self.submodules, "adcif%d" % nadc, adcif)
self.clock_domains.cd_data = ClockDomain()
self.comb += self.cd_data.clk.eq(self.adc_axis_clk)
self.comb += self.cd_data.rst.eq(self.adc_axis_rst)
self.axi_lite = axi.Interface(data_width=32,
address_width=self.axi_width)
self.csr = csr_bus.Interface(data_width=32,
address_width=self.csr_width)
self.submodules.axi2csr = axi.AXILite2CSR(bus_axi=self.axi_lite,
bus_csr=self.csr)
self.submodules.csrbankarray = csr_bus.CSRBankArray(
self,
self._get_csr_map,
data_width=32,
address_width=self.csr_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.csr, self.csrbankarray.get_buses())
self.ios = set()
for i in self.axi_lite, self.offsetdac_mux, self.offsetdac_spi:
self.ios |= set(i.flatten())
self.ios |= set([self.debug, self.adc_axis_clk, self.adc_axis_rst])
for nadc in range(num_adcs):
for i in "adc%d", "adc%d_tdata", "adc%d_tvalid", "adc%d_tready", "adc%d_tlast":
self.ios.add(getattr(self, i % nadc))
def __init__(self,
platform,
clk_freq,
cpu_type="vexriscv",
cpu_reset_address=0x00000000,
cpu_variant=None,
integrated_rom_size=0,
integrated_rom_init=[],
integrated_sram_size=4096,
integrated_sram_init=[],
integrated_main_ram_size=0,
integrated_main_ram_init=[],
shadow_base=0x80000000,
csr_data_width=8,
csr_address_width=14,
with_uart=True,
uart_name="serial",
uart_baudrate=115200,
uart_stub=False,
ident="",
ident_version=False,
wishbone_timeout_cycles=1e6,
with_timer=True,
with_ctrl=True):
self.config = dict()
self.platform = platform
self.clk_freq = clk_freq
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# FIXME: RocketChip reserves the first 256Mbytes for internal use
# remap rom to 0x10000000, sram to 0x20000000
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x20000000
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
# Support the old style which used underscore for separator
if cpu_variant is None:
cpu_variant = "standard"
cpu_variant = cpu_variant.replace('_', '+')
# Check for valid CPU variants.
cpu_variant_processor, *cpu_variant_ext = cpu_variant.split('+')
for key, values in CPU_VARIANTS.items():
if cpu_variant_processor not in [
key,
] + values:
continue
self.cpu_variant = key
break
else:
raise InvalidCPUVariantError(cpu_variant)
# Check for valid CPU extensions.
for ext in sorted(cpu_variant_ext):
if ext not in CPU_VARIANTS_EXTENSIONS:
raise InvalidCPUExtensionError(cpu_variant)
self.cpu_variant += "+" + ext
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.shadow_base = shadow_base
self.wishbone_timeout_cycles = wishbone_timeout_cycles
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self._memory_regions = [] # list of (name, origin, length)
self._csr_regions = [
] # list of (name, origin, busword, csr_list/Memory)
self._constants = [] # list of (name, value)
self._wb_masters = []
self._wb_slaves = []
self._csr_masters = []
# add user csrs
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
if cpu_type is not None:
if cpu_type == "lm32":
self.add_cpu(
lm32.LM32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(
mor1kx.MOR1KX(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(
picorv32.PicoRV32(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(
vexriscv.VexRiscv(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(
minerva.Minerva(platform, self.cpu_reset_address,
self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(
rocket.RocketRV64(platform, self.cpu_reset_address,
self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_csr("cpu", allow_user_defined=True)
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# add cpu reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# add user interrupts
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
self.config["CPU_TYPE"] = str(cpu_type).upper()
if self.cpu_variant:
self.config["CPU_VARIANT"] = str(cpu_type).upper()
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size,
read_only=True,
init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size,
init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus,
integrated_sram_size)
# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(
integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"],
self.main_ram.bus, integrated_main_ram_size)
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.add_constant("CSR_DATA_WIDTH", csr_data_width)
self.register_mem("csr", self.soc_mem_map["csr"],
self.wishbone2csr.wishbone)
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
self.submodules.uart_phy = uart.RS232PHY(
platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(
self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
self.add_constant("SYSTEM_CLOCK_FREQUENCY", int(clk_freq))
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
def __init__(self, platform, core_config, **kwargs):
platform.add_extension(get_common_ios())
# Parameters -------------------------------------------------------------------------------
sys_clk_freq = core_config["sys_clk_freq"]
cpu_type = core_config["cpu"]
csr_expose = core_config.get("csr_expose", False)
csr_align = core_config.get("csr_align", 32)
if cpu_type is None:
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 0
kwargs["l2_size"] = 0
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = False
kwargs["with_wishbone"] = (cpu_type != None)
else:
kwargs["l2_size"] = 0
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, sys_clk_freq,
cpu_type=cpu_type,
csr_alignment=csr_align,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = LiteDRAMCRG(platform, core_config)
# DRAM -------------------------------------------------------------------------------------
platform.add_extension(get_dram_ios(core_config))
assert core_config["memtype"] in ["DDR2", "DDR3"]
self.submodules.ddrphy = core_config["sdram_phy"](
platform.request("ddram"),
memtype=core_config["memtype"],
nphases=4 if core_config["memtype"] == "DDR3" else 2,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=core_config["iodelay_clk_freq"],
cmd_latency=core_config["cmd_latency"])
self.add_constant("CMD_DELAY", core_config["cmd_delay"])
if core_config["memtype"] == "DDR3":
self.ddrphy.settings.add_electrical_settings(
rtt_nom=core_config["rtt_nom"],
rtt_wr=core_config["rtt_wr"],
ron=core_config["ron"])
sdram_module = core_config["sdram_module"](sys_clk_freq,
"1:4" if core_config["memtype"] == "DDR3" else "1:2")
controller_settings = controller_settings=ControllerSettings(
cmd_buffer_depth=core_config["cmd_buffer_depth"])
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=controller_settings)
# DRAM Initialization ----------------------------------------------------------------------
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.comb += [
platform.request("init_done").eq(self.ddrctrl.init_done.storage),
platform.request("init_error").eq(self.ddrctrl.init_error.storage)
]
# CSR port ---------------------------------------------------------------------------------
if csr_expose:
csr_port = csr_bus.Interface(
address_width=self.csr_address_width,
data_width=self.csr_data_width)
self.add_csr_master(csr_port)
platform.add_extension(get_csr_ios(self.csr_address_width,
self.csr_data_width))
_csr_port_io = platform.request("csr_port", 0)
self.comb += [
csr_port.adr.eq(_csr_port_io.adr),
csr_port.we.eq(_csr_port_io.we),
csr_port.dat_w.eq(_csr_port_io.dat_w),
_csr_port_io.dat_r.eq(csr_port.dat_r),
]
if self.cpu_type == None:
csr_base = core_config.get("csr_base", 0)
self.shadow_base = csr_base;
# User ports -------------------------------------------------------------------------------
self.comb += [
platform.request("user_clk").eq(ClockSignal()),
platform.request("user_rst").eq(ResetSignal())
]
if core_config["user_ports_type"] == "native":
for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port()
platform.add_extension(get_native_user_port_ios(i,
user_port.address_width,
user_port.data_width))
_user_port_io = platform.request("user_port", i)
self.comb += [
# cmd
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),
_user_port_io.wdata_ready.eq(user_port.wdata.ready),
user_port.wdata.we.eq(_user_port_io.wdata_we),
user_port.wdata.data.eq(_user_port_io.wdata_data),
# rdata
_user_port_io.rdata_valid.eq(user_port.rdata.valid),
user_port.rdata.ready.eq(_user_port_io.rdata_ready),
_user_port_io.rdata_data.eq(user_port.rdata.data),
]
elif core_config["user_ports_type"] == "wishbone":
for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port()
wb_port = wishbone.Interface(
user_port.data_width,
user_port.address_width)
wishbone2native = LiteDRAMWishbone2Native(wb_port, user_port)
self.submodules += wishbone2native
platform.add_extension(get_wishbone_user_port_ios(i,
len(wb_port.adr),
len(wb_port.dat_w)))
_wb_port_io = platform.request("user_port", i)
self.comb += [
wb_port.adr.eq(_wb_port_io.adr),
wb_port.dat_w.eq(_wb_port_io.dat_w),
_wb_port_io.dat_r.eq(wb_port.dat_r),
wb_port.sel.eq(_wb_port_io.sel),
wb_port.cyc.eq(_wb_port_io.cyc),
wb_port.stb.eq(_wb_port_io.stb),
_wb_port_io.ack.eq(wb_port.ack),
wb_port.we.eq(_wb_port_io.we),
_wb_port_io.err.eq(wb_port.err),
]
elif core_config["user_ports_type"] == "axi":
for i in range(core_config["user_ports_nb"]):
user_port = self.sdram.crossbar.get_port()
axi_port = LiteDRAMAXIPort(
user_port.data_width,
user_port.address_width + log2_int(user_port.data_width//8),
core_config["user_ports_id_width"])
axi2native = LiteDRAMAXI2Native(axi_port, user_port)
self.submodules += axi2native
platform.add_extension(get_axi_user_port_ios(i,
axi_port.address_width,
axi_port.data_width,
core_config["user_ports_id_width"]))
_axi_port_io = platform.request("user_port", i)
self.comb += [
# aw
axi_port.aw.valid.eq(_axi_port_io.aw_valid),
_axi_port_io.aw_ready.eq(axi_port.aw.ready),
axi_port.aw.addr.eq(_axi_port_io.aw_addr),
axi_port.aw.burst.eq(_axi_port_io.aw_burst),
axi_port.aw.len.eq(_axi_port_io.aw_len),
axi_port.aw.size.eq(_axi_port_io.aw_size),
axi_port.aw.id.eq(_axi_port_io.aw_id),
# w
axi_port.w.valid.eq(_axi_port_io.w_valid),
_axi_port_io.w_ready.eq(axi_port.w.ready),
axi_port.w.last.eq(_axi_port_io.w_last),
axi_port.w.strb.eq(_axi_port_io.w_strb),
axi_port.w.data.eq(_axi_port_io.w_data),
# b
_axi_port_io.b_valid.eq(axi_port.b.valid),
axi_port.b.ready.eq(_axi_port_io.b_ready),
_axi_port_io.b_resp.eq(axi_port.b.resp),
_axi_port_io.b_id.eq(axi_port.b.id),
# ar
axi_port.ar.valid.eq(_axi_port_io.ar_valid),
_axi_port_io.ar_ready.eq(axi_port.ar.ready),
axi_port.ar.addr.eq(_axi_port_io.ar_addr),
axi_port.ar.burst.eq(_axi_port_io.ar_burst),
axi_port.ar.len.eq(_axi_port_io.ar_len),
axi_port.ar.size.eq(_axi_port_io.ar_size),
axi_port.ar.id.eq(_axi_port_io.ar_id),
# r
_axi_port_io.r_valid.eq(axi_port.r.valid),
axi_port.r.ready.eq(_axi_port_io.r_ready),
_axi_port_io.r_last.eq(axi_port.r.last),
_axi_port_io.r_resp.eq(axi_port.r.resp),
_axi_port_io.r_data.eq(axi_port.r.data),
_axi_port_io.r_id.eq(axi_port.r.id),
]
else:
raise ValueError("Unsupported port type: {}".format(core_config["user_ports_type"]))