def packet_description(dw): param_layout = packet_header.get_layout() payload_layout = [ ("data", dw), ("error", dw//8) ] return EndpointDescription(payload_layout, param_layout)
def eth_etherbone_packet_user_description(dw): param_layout = etherbone_packet_header.get_layout() param_layout = _remove_from_layout(param_layout, "magic", "portsize", "addrsize", "version") param_layout += eth_udp_user_description(dw).param_layout payload_layout = [("data", dw), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def udp_fragmenter_description(dw): param_layout = [ ("length", 32), ] payload_layout = fragmenter_header.get_layout() + [ ("data", dw), ] return EndpointDescription(payload_layout, param_layout)
def packet_description(dw): param_layout = __class__.get_header(dw).get_layout() payload_layout = [ ("data", dw), ("last_be", dw//8), ("error", dw//8) ] return EndpointDescription(payload_layout, param_layout)
def kyokkoStreamDesc(lanes=4): from litex.soc.interconnect.stream import EndpointDescription return EndpointDescription( [ ("data", 64 * lanes), # ("keep", (64 * lanes) // 8) ] )
def packet_user_description(dw): param_layout = __class__.get_header(dw).get_user_layout() # param_layout = _remove_from_layout(param_layout, "magic", "portsize", "addrsize", "version") param_layout += eth_udp_user_description(dw).param_layout payload_layout = [ ("data", dw), ("last_be", dw//8), ("error", dw//8) ] return EndpointDescription(payload_layout, param_layout)
def user_description(dw): param_layout = [ ("dst", 8), ("length", 32) ] payload_layout = [ ("data", dw), ("error", dw//8) ] return EndpointDescription(payload_layout, param_layout)
def __init__(self, dw=32, max_latency=65536): self.sink = sink = Endpoint(K2MMPacket.packet_user_description(dw)) self.source = source = Endpoint(K2MMPacket.packet_user_description(dw)) # # # self.submodules.tfg = tfg = TestFrameGenerator(data_width=dw) self.sink_ctrl = Endpoint(tfg.sink_ctrl.description) self.submodules.tfc = tfc = TestFrameChecker(dw=dw) self.comb += [sink.connect(tfc.sink), tfg.source.connect(source)] self.latency = latency = Signal(max=max_latency) fsm = FSM(reset_state="STOP") fsm.act( "STOP", self.sink_ctrl.connect(tfg.sink_ctrl), If( tfg.sink_ctrl.valid & tfg.sink_ctrl.ready, NextState("COUNT_LATENCY"), NextValue(latency, 0), ), ) fsm.act( "COUNT_LATENCY", NextValue(latency, latency + 1), tfc.source_tf_status.ready.eq(1), If(tfc.source_tf_status.valid == 1, NextState("STOP")), ) self.submodules += fsm self.source_status = Endpoint( EndpointDescription( tfc.source_tf_status.description.payload_layout + [("latency", latency.nbits)], tfc.source_tf_status.description.param_layout)) self.comb += [ tfc.source_tf_status.connect(self.source_status, omit={"latency"}), self.source_status.latency.eq(latency), self.source_status.ready.eq(1) ]
def eth_etherbone_record_description(dw): param_layout = etherbone_record_header.get_layout() payload_layout = [("data", dw), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def eth_udp_user_description(dw): param_layout = [("src_port", 16), ("dst_port", 16), ("ip_address", 32), ("length", 16)] payload_layout = [("data", dw), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def eth_icmp_user_description(dw): param_layout = icmp_header.get_layout() + [("ip_address", 32), ("length", 16)] payload_layout = [("data", dw), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def eth_ipv4_user_description(dw): param_layout = [("length", 16), ("protocol", 8), ("ip_address", 32)] payload_layout = [("data", dw), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def phy_description(dw): layout = [("data", dw)] return EndpointDescription(layout)
def eth_udp_description(dw): param_layout = udp_header.get_layout() payload_layout = [("data", dw), ("last_be", dw // 8), ("error", dw // 8)] return EndpointDescription(payload_layout, param_layout)
def eth_etherbone_mmap_description(dw): param_layout = [("we", 1), ("count", 8), ("base_addr", 32), ("be", dw // 8)] payload_layout = [("addr", 32), ("data", dw)] return EndpointDescription(payload_layout, param_layout)
def eth_phy_description(dw): payload_layout = [("data", dw), ("last_be", dw // 8), ("error", dw // 8)] return EndpointDescription(payload_layout)
def eth_tty_description(dw): payload_layout = [("data", dw)] return EndpointDescription(payload_layout)
def eth_mac_description(dw): payload_layout = mac_header.get_layout() + [("data", dw), ("last_be", dw // 8), ("error", dw // 8)] return EndpointDescription(payload_layout)
def user_description(dw): layout = [("data", dw), ("dst", 8), ("length", 32)] return EndpointDescription(layout)
def __init__(self, dat, clk, sys_clk_freq): if type(dat) != TSTriple: t = TSTriple() self.specials += t.get_tristate(dat) dat = t if type(clk) != TSTriple: t = TSTriple() self.specials += t.get_tristate(clk) clk = t dat_i = Signal() clk_i = Signal() self.specials += [ MultiReg(dat.i, dat_i), MultiReg(clk.i, clk_i), ] self.comb += [ dat.oe.eq(0), clk.oe.eq(0), ] fields = [ CSRField(name="data", size=8, description="Received data"), CSRField(name="valid", description="Data valid"), ] self.rx = CSRStatus(32, description="Receive register", fields=fields) self.submodules.ev = EventManager() self.ev.data = EventSourceLevel() self.ev.finalize() layout = EndpointDescription([("data", 8)]) self.submodules.rx_fifo = rx_fifo = SyncFIFO(layout, 16) self.comb += [ self.rx.fields.data.eq(rx_fifo.source.data), self.rx.fields.valid.eq(rx_fifo.source.valid), rx_fifo.source.ready.eq(self.rx.we), self.ev.data.trigger.eq(rx_fifo.source.valid), ] # One transaction lasts about 1.1ms, so we can consider the bus idle # after 1.5ms of high CLK state idle_ticks = int(sys_clk_freq * 1.5e-3) reset = Signal() self.submodules.reset_timer = WaitTimer(idle_ticks) self.comb += [ self.reset_timer.wait.eq(clk_i), reset.eq(self.reset_timer.done), ] # Stabilize CLK clk_stable = Signal() prev_clk = Signal() self.sync += prev_clk.eq(clk_i) self.submodules.clk_timer = WaitTimer(10) self.comb += [ self.clk_timer.wait.eq(prev_clk == clk_i), clk_stable.eq(self.clk_timer.done), ] clk_pulse = Signal() clk_stable_d = Signal() self.sync += [ clk_stable_d.eq(clk_stable), clk_pulse.eq(clk_stable & ~clk_stable_d) ] bits = Signal(11) bitcount = Signal(4) parity = reduce(xor, bits) self.sync += [ rx_fifo.sink.valid.eq(0), If(reset, bitcount.eq(0), bits.eq(0), ).Else( If(clk_pulse & ~clk_i, bits.eq(Cat(bits[1:], dat_i)), bitcount.eq(bitcount + 1) ).Elif(bitcount == 11, If(bits[10] & ~bits[0] & ~parity, rx_fifo.sink.data.eq(bits[1:9]), rx_fifo.sink.valid.eq(1), ), bitcount.eq(0), bits.eq(0) ) ) ]