def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
def __init__(self,
toolchain="trellis",
sys_clk_freq=int(48e6),
sdram_module_cls="AS4C32M8",
**kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCCore ---------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Hackaday Badge",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
sys_clk_freq)
self.add_sdram("sdram",
phy=self.sdrphy,
module=AS4C32M8(sys_clk_freq, "1:1"),
l2_cache_size=kwargs.get("l2_size", 8192))
def __init__(self, toolchain="trellis", sys_clk_freq=int(48e6), sdram_module_cls="AS4C32M8", **kwargs):
platform = hadbadge.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = AS4C32M8(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
sdram_module.timing_settings)
def __init__(self, debug=True, sdram_module_cls="AS4C32M8", **kwargs):
platform = hadbadge.Platform()
clk_freq = int(48e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
integrated_rom_size=16384,
integrated_sram_size=65536,
wishbone_timeout_cycles=1e9,
**kwargs)
self.submodules.crg = _CRG(self.platform, sys_clk_freq=clk_freq)
# Add a "Version" module so we can see what version of the board this is.
# self.submodules.version = Version("proto2", [
# (0x02, "proto2", "Prototype Version 2 (red)")
# ], 0)
# Add a "USB" module to let us debug the device.
# usb_pads = platform.request("usb")
# usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
# self.submodules.usb = ClockDomainsRenamer({
# "usb_48": "clk48",
# "usb_12": "clk12",
# })(DummyUsb(usb_iobuf, debug=debug, product="Hackaday Supercon Badge", cdc=True))
#
# if debug:
# self.add_wb_master(self.usb.debug_bridge.wishbone)
#
# if self.cpu_type is not None:
# self.register_mem("vexriscv_debug", 0xb00f0000, self.cpu.debug_bus, 0x200)
# self.cpu.use_external_variant("rtl/VexRiscv_HaD_Debug.v")
# elif self.cpu_type is not None:
# self.cpu.use_external_variant("rtl/VexRiscv_HaD.v")
# Add the 16 MB SPI flash as XIP memory at address 0x03000000
# if not is_sim:
# # flash = SpiFlashDualQuad(platform.request("spiflash4x"), dummy=5)
# # flash.add_clk_primitive(self.platform.device)
# # self.submodules.lxspi = flash
# # self.register_mem("spiflash", 0x03000000, self.lxspi.bus, size=16 * 1024 * 1024)
# self.submodules.picorvspi = flash = PicoRVSpi(self.platform, pads=platform.request("spiflash"), size=16 * 1024 * 1024)
# self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=self.picorvspi.size)
# # Add the 16 MB SPI RAM at address 0x40000000 # Value at 40010000: afbfcfef
# reset_cycles = 2**14-1
# ram = SpiRamDualQuad(platform.request("spiram4x", 0), platform.request("spiram4x", 1), dummy=5, reset_cycles=reset_cycles, qpi=True)
# self.submodules.ram = ram
# self.register_mem("main_ram", self.mem_map["main_ram"], self.ram.bus, size=16 * 1024 * 1024)
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=2)
sdram_module = getattr(litedram_modules, sdram_module_cls)(clk_freq,
"1:1")
self.register_sdram(self.sdrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# Let us reboot the device
# self.submodules.reboot = Reboot(platform.request("programn"))
# Add a Messible for sending messages to the host
# self.submodules.messible = Messible()
# Add an LCD so we can see what's up
# self.submodules.lcdif = LCDIF(platform.request("lcd"))
# Ensure timing is correctly set up
self.platform.toolchain.build_template[
1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5
self.platform.toolchain.freq_constraints["sys"] = 48