def __init__(self,
bios_flash_offset,
sys_clk_freq=int(24e6),
with_led_chaser=True,
with_video_terminal=False,
**kwargs):
platform = muselab_icesugar.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant
if kwargs.get("cpu_type", "vexriscv") == "vexriscv":
kwargs["cpu_variant"] = "lite"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Muselab iCESugar",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=64 * kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * kB))
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q64FV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x",
module=W25Q64FV(Codes.READ_1_1_1),
with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.bus.regions["spiflash"].origin +
bios_flash_offset,
size=32 * kB,
linker=True))
self.cpu.set_reset_address(self.bus.regions["rom"].origin)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
led_pads = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=led_pads,
sys_clk_freq=sys_clk_freq)
def __init__(self,
bios_flash_offset,
sys_clk_freq=int(24e6),
with_video_terminal=False,
**kwargs):
platform = muselab_icesugar.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_variant"] = "lite"
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Muselab iCESugar",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
self.submodules.spram = Up5kSPRAM(size=64 * kB)
self.bus.add_slave("sram", self.spram.bus, SoCRegion(size=64 * kB))
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
size=32 * kB,
linker=True))
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=led_pads,
sys_clk_freq=sys_clk_freq)