def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False, **kwargs): platform = pano_logic_g2.Platform(revision=revision) if with_etherbone: sys_clk_freq = int(125e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Pano Logic G2", ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone) # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: self.submodules.ethphy = LiteEthPHY( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth"), clk_freq = sys_clk_freq, with_hw_init_reset = False) self.add_csr("ethphy") if with_ethernet: self.add_ethernet(phy=self.ethphy) if with_etherbone: self.add_etherbone(phy=self.ethphy) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds")
def __init__(self, sys_clk_freq=int(50e6), **kwargs): platform = pano_logic_g2.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq) # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads=Cat(*[platform.request("user_led", i) for i in range(3)]), sys_clk_freq=sys_clk_freq) self.add_csr("leds") # Take Ethernet Phy out of reset for SYSCLK of 125 Mhz gmii_rst_n = platform.request("gmii_rst_n") self.comb += [gmii_rst_n.eq(1)]