def txn(self, ch, n, t):
"write n elements to tx space"
if ch == 'tx1': # not for enhanced mode!
txStart = self.TX1
mtestOpt = ""
elif ch == 'tx2': # not for enhanced mode!
txStart = self.TX2
mtestOpt = ""
elif ch == 'tx12':
txStart = self.TX12
mtestOpt = "-w"
else:
self.cpu.ut.fail("*** illegal ch=%d" % ch)
start = self.base + txStart
end = start + self.TRX_SIZE - 1
if n != 0xffffffff:
end = start + (n * 2)
log.info("write %d %s to %s space" % (n, tInfo(t), ch))
else:
log.info("write %s to entire %s space" % (tInfo(t), ch))
cmmd = "mtest \"0x%x 0x%x -o=2 -q=%d -t=%s %s\"" % \
(start, end, mtestMaxErr, t, mtestOpt)
execCmdSucc(self.cpu.cons, cmmd, 0)
def skipIfBrd(self, brd, task):
"skip task if the specified board"
if self.type == brd:
log.info("%s skipped for board %s=%s" % \
(task, self.idStr, self.type))
return 1
return 0
def checkClrTxstat(self, ch, expect):
"check and clear TXSTAT"
log.info("check and clear TXSTAT%d" % ch)
cmmd = "a404TxstatGetClr( 0x%x, %d, %d )" % \
(self.base, self.enh, ch)
execCmdSucc(self.cpu.cons, cmmd, expect)
def detectBoard(self):
"detect board"
log.info("detect %s" % self.idStr)
cmmd = "a404DetectA24(0x%x, 0x%x)" % \
(a15_A24D16_base, self.scarte)
ret = execCmdFail(self.cpu.cons, cmmd, -1)
# CME board?
if ret == 0:
self.type = 'OLD_CME'
self.enh = 0
self.defaultSpace = 'A24D16'
self.accTbl = ['b', 'w']
self.accOpt = 'bw'
elif ret == 1:
self.type = 'A404_COMP_MODE'
self.enh = 0
self.defaultSpace = 'A24D32'
self.accTbl = ['b', 'w', 'l']
self.accOpt = 'bwl'
elif ret == 2:
self.type = 'A404_ENH_MODE'
self.enh = 1
self.defaultSpace = 'A24D32'
self.accTbl = ['b', 'w', 'l']
self.accOpt = 'bwl'
else:
self.cpu.ut.fail("*** a404DetectA24 returns unknown value")
def disableHwLoop(self):
"disable HW loop-back"
log.info("disable TX1->RX1, TX2->RX2 HW loop (enable external lanes)")
for ch in [1, 2]:
cmmd = "a404ByteRegSetmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(self.base, self.enh, ch, RXCTRL, RXCTRL_LOOP_NO)
execCmdSucc(self.cpu.cons, cmmd, 0)
def test_610_TRXC_A32(self):
log.warn("=== A32 TRX command: TX1/TX2 transfer test ===")
brd = self.brd1
cpu = brd.cpu
# A404_ENH_MODE only
if brd.skipIfNotBrd('A404_ENH_MODE', 'test'):
return
brd.enableA32()
brd.initBoard(0)
log.info("transfer commands (TXCOM1-->RXCOM2)")
for cmmd in self.cmmdTbl:
brd.sendCmd(1, cmmd)
brd.recvVeriCmd(2, cmmd)
log.info("transfer commands (TXCOM2-->RXCOM1)")
for cmmd in self.cmmdTbl:
brd.sendCmd(2, cmmd)
brd.recvVeriCmd(1, cmmd)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
brd.disableA32()
def disableTX1TX2(self):
"disable TX1/TX2 transmitter"
log.info("disable TX1/TX2 transmitter")
for ch in [1, 2]:
cmmd = "a404ByteRegSetmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(self.base, self.enh, ch, TXCTRL, TXCTRL_TXENBL)
execCmdSucc(self.cpu.cons, cmmd, 0)
def test_315_SDRAM_A32BLK(self):
log.warn("=== A32BLK access to SDRAM (A404 enhanced mode) ===")
brd = self.brd1
cpu = brd.cpu
# A404_ENH_MODE only
if brd.skipIfNotBrd('A404_ENH_MODE', 'test'):
return
brd.enableA32()
for spacename, offs in self.sdramRxTbl(brd).items():
startaddr = brd.vmeAddr + offs
endaddr = startaddr + brd.TRX_SIZE - 1
log.info("access %s" % spacename)
# D32
cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a32d32,10\"" % \
(startaddr, endaddr, mtestMaxErr)
execCmdSucc(cpu.cons, cmmd, 0)
# D64
cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a32d64,10\"" % \
(startaddr, endaddr, mtestMaxErr)
execCmdSucc(cpu.cons, cmmd, 0)
brd.disableA32()
def clrTxstat(self, ch):
"clear TXSTAT"
log.info("clear TXSTAT%d" % ch)
cmmd = "a404TxstatGetClr( 0x%x, %d, %d )" % \
(self.base, self.enh, ch)
getShellVarValue(self.cpu.cons, cmmd)
def getClrRxstat(self, ch):
"get and clear RXSTAT"
log.info("get and clear RXSTAT%d" % ch)
cmmd = "a404RxstatGetClr( 0x%x, %d, %d )" % \
(self.base, self.enh, ch)
return getShellVarValue(self.cpu.cons, cmmd)
def rx_clr(self, ch, t, clear):
"read/clear rx space"
if ch == 'rx1':
rxStart = self.RX1
elif ch == 'rx2':
rxStart = self.RX2
elif ch == 'tx1': # not for enhanced mode!
rxStart = self.TX1
elif ch == 'tx2': # not for enhanced mode!
rxStart = self.TX2
elif ch == 'tx12':
rxStart = self.TX12
else:
self.cpu.ut.fail("*** illegal ch=%d" % ch)
start = self.base + rxStart
size = self.TRX_SIZE
end = start + size - 1
if clear:
cmmd = "memset( 0x%x, 0x00, 0x%x )" % \
(start, size)
log.info("clear data in %s space" % \
ch )
execCmdFail(self.cpu.cons, cmmd, 0)
else:
cmmd = "mtest \"0x%x 0x%x -o=2 -q=%d -t=%s -v\"" % \
(start, end, mtestMaxErr, t)
log.info("read and verify %s from %s space" % \
(tInfo(t), ch) )
execCmdSucc(self.cpu.cons, cmmd, 0)
def checkClrRxstat12(self, expect):
"check and clear RXSTAT1/RXSTAT2"
log.info("check and clear RXSTAT1/RXSTAT2")
for ch in [1, 2]:
cmmd = "a404RxstatGetClr( 0x%x, %d, %d )" % \
(self.base, self.enh, ch)
execCmdSucc(self.cpu.cons, cmmd, expect)
def txBlk(self, mod):
"blk write to tx space"
start = self.vmeAddr + self.TX12
end = start + self.TRX_SIZE - 1
log.info("blk write %s to entire TX12 space" % (mod))
cmmd = "mtest \"0x%x 0x%x -o=2 -q=%d -t=w -m=%s,10\"" % \
(start, end, mtestMaxErr, mod)
execCmdSucc(self.cpu.cons, cmmd, 0)
def test_200_VMEREGS_A24(self):
log.warn("=== A24 access to VME-Registers ===")
brd = self.brd1
cpu = brd.cpu
for regname, offs in self.vmeRegTbl.items():
startaddr = brd.base + brd.RXC + offs
cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \
(startaddr, startaddr+1, mtestMaxErr, brd.accOpt)
log.info("access %s" % regname)
execCmdSucc(cpu.cons, cmmd, 0)
def initBoard(self, hwloop):
"init board"
if hwloop == 1:
info = "enabled"
else:
info = "disabled"
log.info("initialize %s (HW-LOOP %s)" % (self.idStr, info))
cmmd = "a404Init( 0x%x, %d, %d )" % \
(self.base, self.enh, hwloop)
execCmdSucc(self.cpu.cons, cmmd, 0)
def test_710_IRQ_A24(self):
log.warn("=== A24 IRQ stress test ===")
brd = self.brd1
cpu = brd.cpu
brd.initBoard(0)
log.info("IRQ test:")
cmmd = "a404IrqTest( 0x%x, %d )" % (brd.base, brd.enh)
execCmdSucc(cpu.cons, cmmd, 0)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
def test_300_SDRAM_A24(self):
log.warn("=== A24 access to SDRAM ===")
brd = self.brd1
cpu = brd.cpu
for spacename, offs in self.sdramRxTbl(brd).items():
startaddr = brd.base + offs
endaddr = startaddr + brd.TRX_SIZE - 1
cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=%s\"" % \
(startaddr, endaddr, mtestMaxErr, brd.accOpt)
log.info("access %s" % spacename)
execCmdSucc(cpu.cons, cmmd, 0)
def test_800_DISCON(self):
log.warn("=== Disconnection test: get TX/RX status ===")
brd = self.brd1
cpu = brd.cpu
brd.initBoard(0)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
userReady("Please remove the TX1->RX2, TX2->RX1 wires")
for ch in [1, 2]:
ret = brd.getClrRxstat(ch)
log.info("check RXSTAT%d for !CONNECTED" % ch)
if ret & RXSTAT_CONNECT == RXSTAT_CONNECT:
log.error(cmmd + ' : failed')
self.fail("RXSTAT::CONNECTED bit set")
# not OLD_CME
if brd.skipIfBrd('OLD_CME', 'TX status check') == 0:
brd.clrTxstat(1)
brd.clrTxstat(2)
# write words to tx1/2
brd.tx('tx12', 'w')
brd.checkClrTxstat(1, 0x01)
brd.checkClrTxstat(2, 0x01)
brd.checkClrTxstat(1, 0x00)
brd.checkClrTxstat(2, 0x00)
for loop in [0, 1]:
for n in range(0, 5):
brd.initBoard(loop)
for ch in [1, 2]:
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR == RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit set")
if ret & RXSTAT_DATALOST == RXSTAT_DATALOST:
self.fail("RXSTAT::RXSTAT_DATALOST bit set")
userReady("Please re-plug the TX1->RX2, TX2->RX1 wires")
for ch in [1, 2]:
ret = brd.getClrRxstat(ch)
log.info("check RXSTAT%d for CONNECTED" % ch)
if ret & RXSTAT_CONNECT != RXSTAT_CONNECT:
log.error(cmmd + ' : failed')
self.fail("RXSTAT::CONNECTED bit not set")
def test_820_RXFIFO(self):
log.warn("=== Receiver Fifo test: get RX status ===")
brd = self.brd1
cpu = brd.cpu
# A404 only
if brd.skipIfBrd('OLD_CME', 'test'):
return
brd.initBoard(0)
for rxCh in (1, 2):
log.info("RX%d: Receiver Fifo test" % rxCh)
cmmd = "a404RxFifoTest( 0x%x, %d, %d )" % \
(brd.base, brd.enh, rxCh)
execCmdSucc(cpu.cons, cmmd, 0)
def rxBlk(self, ch, mod):
"blk read rx space"
if ch == 'rx1':
rxStart = self.RX1
elif ch == 'rx2':
rxStart = self.RX2
else:
self.cpu.ut.fail("*** illegal ch=%d" % ch)
start = self.vmeAddr + rxStart
end = start + self.TRX_SIZE - 1
log.info("blk read %s from entire %s space" % (mod, ch))
cmmd = "mtest \"0x%x 0x%x -o=2 -q=%d -t=v -m=%s,10 -v\"" % \
(start, end, mtestMaxErr, mod)
execCmdSucc(self.cpu.cons, cmmd, 0)
def test_720_IRQ_A32(self):
log.warn("=== A32 IRQ stress test ===")
brd = self.brd1
cpu = brd.cpu
# A404_ENH_MODE only
if brd.skipIfNotBrd('A404_ENH_MODE', 'test'):
return
brd.enableA32()
brd.initBoard(0)
log.info("IRQ test:")
cmmd = "a404IrqTest( 0x%x, %d )" % (brd.base, brd.enh)
execCmdSucc(cpu.cons, cmmd, 0)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
brd.disableA32()
def test_210_VMEREGS_A32(self):
log.warn("=== A32 access to VME-Registers ===")
brd = self.brd1
cpu = brd.cpu
# A404_ENH_MODE only
if brd.skipIfNotBrd('A404_ENH_MODE', 'test'):
return
brd.enableA32()
for regname, offs in self.vmeRegTbl.items():
startaddr = brd.base + brd.RXC + offs
cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \
(startaddr, startaddr+1, mtestMaxErr, brd.accOpt)
log.info("access %s" % regname)
execCmdSucc(cpu.cons, cmmd, 0)
brd.disableA32()
def test_310_SDRAM_A32(self):
log.warn("=== A32 access to SDRAM (A404 enhanced mode) ===")
brd = self.brd1
cpu = brd.cpu
# A404_ENH_MODE only
if brd.skipIfNotBrd('A404_ENH_MODE', 'test'):
return
brd.enableA32()
for spacename, offs in self.sdramRxTbl(brd).items():
startaddr = brd.base + offs
endaddr = startaddr + brd.TRX_SIZE - 1
cmmd = "mtest \"0x%x 0x%x -n=3 -o=2 -q=%d -t=%s\"" % \
(startaddr, endaddr, mtestMaxErr, brd.accOpt)
log.info("access %s" % spacename)
execCmdSucc(cpu.cons, cmmd, 0)
brd.disableA32()
def _TRXD_BASIC(self, loop):
brd = self.brd1
cpu = brd.cpu
brd.initBoard(loop)
if loop:
ret = 1
else:
ret = 2
if brd.enh == 1:
ret = 0
log.info("check basic data transfer")
cmmd = "a404CheckLanes( 0x%x, %d )" % \
(brd.base, brd.enh )
execCmdSucc(cpu.cons, cmmd, ret)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
if loop:
brd.disableHwLoop()
def test_305_SDRAM_A24BLK(self):
log.warn("=== A24BLK access to SDRAM ===")
brd = self.brd1
cpu = brd.cpu
# A404 only
if brd.skipIfBrd('OLD_CME', 'test'):
return
for spacename, offs in self.sdramRxTbl(brd).items():
startaddr = brd.vmeAddr + offs
endaddr = startaddr + brd.TRX_SIZE - 1
log.info("access %s" % spacename)
# D16
cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a24d16,10\"" % \
(startaddr, endaddr, mtestMaxErr)
execCmdSucc(cpu.cons, cmmd, 0)
# D32
cmmd = "mtest \"0x%x 0x%x -n=2 -o=2 -q=%d -t=v -m=a24d32,10\"" % \
(startaddr, endaddr, mtestMaxErr)
execCmdSucc(cpu.cons, cmmd, 0)
def _TRXC_A24(self, loop):
brd = self.brd1
cpu = brd.cpu
brd.initBoard(loop)
if loop:
srcTbl = [1, 2]
sinkTbl = [1, 2]
else:
srcTbl = [1, 2]
sinkTbl = [2, 1]
for src, sink in zip(srcTbl, sinkTbl):
log.info("transfer commands (TXCOM%d-->RXCOM%d)" % (src, sink))
for cmmd in self.cmmdTbl:
brd.sendCmd(src, cmmd)
brd.recvVeriCmd(sink, cmmd)
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
if loop:
brd.disableHwLoop()
def membench(self, space, txoff):
"membench to TX12 space"
brd = self.brd1
c = brd.cpu.cons
if txoff:
onOff = 'off'
else:
onOff = 'on'
# A24 space
if space == 'a24':
sglMaxblkTbl = [0x00400, 0x01000, 0x04000, 0x10000, 0x20000]
blkModTbl = ['a24d16', 'a24d32']
log.info("a24d16 single access to TX12 space (tx1/tx2 %s)" % onOff)
brd.setA24Base('A24D16')
for blkSize in sglMaxblkTbl:
c.sendline( "membench2( 0x%x, 0x%x, 0x%x, 0x%x )" \
% (brd.base + brd.TX12, blkSize, blkSize, brd.TRX_SIZE) )
c.expect('value = 0 = 0x0')
c.expect(shPrompt)
brd.setA24Base('A24D32')
# A32 space
else:
sglMaxblkTbl = [
0x00400, 0x01000, 0x04000, 0x10000, 0x40000, 0x100000
]
# a32d64 currently unsupported blkModTbl = ['a32d32','a32d64']
blkModTbl = ['a32d32']
log.info("%sd32 single access to TX12 space (tx1/tx2 %s)" %
(space, onOff))
for blkSize in sglMaxblkTbl:
c.sendline( "membench2( 0x%x, 0x%x, 0x%x, 0x%x )" \
% (brd.base + brd.TX12, blkSize, blkSize, brd.TRX_SIZE) )
c.expect('value = 0 = 0x0')
c.expect(shPrompt)
for mod in blkModTbl:
log.info("%s burst access to TX12 space (tx1/tx2 %s)" %
(mod, onOff))
c.sendline( "vmeblkbench( 0x%x, \"%s\", 0x%x, 0x%x, 0x%x )" \
% (brd.vmeAddr + brd.TX12, mod, 0x400, brd.TRX_SIZE, brd.TRX_SIZE) )
c.expect('value = 0 = 0x0')
c.expect(shPrompt)
def test_810_CRCERR(self):
log.warn("=== CRC error detection test: get RX status ===")
brd = self.brd1
cpu = brd.cpu
brd.initBoard(0)
log.info("TX1/TX2: enable CRC error insertion")
for ch in [1, 2]:
cmmd = "a404ByteRegSetmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(brd.base, brd.enh, ch, TXCTRL, TXCTRL_CRCERR)
execCmdSucc(cpu.cons, cmmd, 0)
# write 2 words to tx1/2
brd.txn('tx12', 2, 'w')
for ch in [1, 2]:
log.info("check RXSTAT%d for RCV_CRC_ERR (and clear)" % ch)
# OLD_CME
if brd.type == 'OLD_CME':
log.info("OLD_CME: FIFO will be emptied by repeating the "
"clear"
"")
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR != RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit not set")
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR == RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit set")
if ret & RXSTAT_DATALOST != RXSTAT_DATALOST:
self.fail("RXSTAT::RXSTAT_DATALOST bit not set")
ret = brd.getClrRxstat(ch)
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR == RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit set")
if ret & RXSTAT_DATALOST == RXSTAT_DATALOST:
self.fail("RXSTAT::RXSTAT_DATALOST bit set")
# A404
else:
log.info("A404: Different behaviour as OLD_CME")
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR != RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit not set")
if ret & RXSTAT_DATALOST != RXSTAT_DATALOST:
self.fail("RXSTAT::RXSTAT_DATALOST bit not set")
ret = brd.getClrRxstat(ch)
if ret & RXSTAT_CRCERR == RXSTAT_CRCERR:
self.fail("RXSTAT::RCV_CRC_ERR bit set")
if ret & RXSTAT_DATALOST == RXSTAT_DATALOST:
self.fail("RXSTAT::RXSTAT_DATALOST bit set")
log.info("TX1/TX2: disable CRC error insertion")
for ch in [1, 2]:
cmmd = "a404ByteRegClrmask( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(brd.base, brd.enh, ch, TXCTRL, TXCTRL_CRCERR)
execCmdSucc(cpu.cons, cmmd, 0)
# write 2 words to tx1/2
brd.txn('tx12', 2, 'w')
brd.checkClrRxstat12(RXSTAT_CONNECT | RXSTAT_FFFULL_NO)
def irqBasicTest(self, txCh, rxCh, irqLev, irqVec):
"IRQ basic test"
brd = self.brd1
cpu = brd.cpu
cmmd = "a404RxSetIrqVector( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, rxCh, irqVec )
log.info("RX%d: set vector=%d" % (rxCh, irqVec))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxIrqEnable( 0x%x, %d, %d, %d, 1 )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: enable level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404InstallIsr( %d, %d )" % \
(irqVec, irqLev)
log.info("CPU: install ISR for vector=%d, enable level=%d" %
(irqVec, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404GetClrIsrCount( %d )" % irqVec
log.info("CPU: get/clr ISR count for vector=%d" % irqVec)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404TxIrqSend( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, txCh, irqLev )
log.info("TX%d: send IRQ with level=%d" % (txCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404GetClrIsrCount( %d )" % irqVec
log.info("CPU: get/clr ISR count for vector=%d" % irqVec)
execCmdSucc(cpu.cons, cmmd, 1)
cmmd = "sysIntDisable( %d )" % irqLev
log.info("CPU: disable level=%d" % irqLev)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxGetIrqPending( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: check for pending level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404TxIrqSend( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, txCh, irqLev )
log.info("TX%d: send IRQ with level=%d" % (txCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxGetIrqPending( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: check for pending level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 1)
cmmd = "a404ByteRegWrite( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(brd.base, brd.enh, rxCh, RXIRQ, 0xff)
log.info("RX%d: clear all pending IRQs" % rxCh)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxGetIrqPending( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: check for pending level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "sysIntEnable( %d )" % irqLev
log.info("CPU: enable level=%d" % irqLev)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404GetClrIsrCount( %d )" % irqVec
log.info("CPU: get/clr ISR count for vector=%d" % irqVec)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxIrqEnable( 0x%x, %d, %d, %d, 0 )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: disable level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404TxIrqSend( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, txCh, irqLev )
log.info("TX%d: send IRQ with level=%d" % (txCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404GetClrIsrCount( %d )" % irqVec
log.info("CPU: get/clr ISR count for vector=%d" % irqVec)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404RxGetIrqPending( 0x%x, %d, %d, %d )" % \
(brd.base, brd.enh, rxCh, irqLev )
log.info("RX%d: check for pending level=%d" % (rxCh, irqLev))
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404ByteRegWrite( 0x%x, %d, %d, 0x%x, 0x%x )" % \
(brd.base, brd.enh, rxCh, RXIRQ, 0xff)
log.info("RX%d: clear all pending IRQs" % rxCh)
execCmdSucc(cpu.cons, cmmd, 0)
cmmd = "a404UnInstallIsr( %d )" % \
(irqVec)
log.info("CPU: uninstall ISR for vector=%d" % (irqVec))
execCmdSucc(cpu.cons, cmmd, 0)
