def bitarray(self):
Now = veri.peek('%s.bitarray' % (self.Path))
if Now != self.Was:
for ii, newBit in enumerate(Now):
oldBit = self.Was[ii]
if newBit != oldBit:
logs.log_info3('catchBitWrite %s bit=%d new=%s' %
(self.Name, 31 - ii, newBit))
self.Was = Now
def dispf(self, Why, SIGS):
List = string.split(SIGS)
res = 'dispf %s = ' % (Why)
for Sig in List:
Val = self.peek1(Sig)
Flt = logs.binary2float(Val)
res += ' %s=%f' % (Sig, Flt)
self.simul.setVar(Sig, Flt)
logs.log_info3('catchInputs %s %s' % (self.Name, res))
def bitarray2(self, Side):
Addr = logs.intx(veri.peek_mem('%s.paddress' % (self.Path), str(0)))
if Side == 'a':
if Addr in self.proga:
Text = self.proga[Addr]
else:
Text = ' a empty'
if Side == 'b':
if Addr in self.progb:
Text = self.progb[Addr]
else:
Text = ' b empty'
Dst = getDst(Text)
a_write_bits0_flag = self.peek('%s0_write_bits0_flag' % Side)
if a_write_bits0_flag == 1:
a0_dst_field = self.peek('%s0_dst_field' % Side)
if a0_dst_field > 0:
abitwdata = self.peek('bitfile.%sbitwdata' % Side)
if a0_dst_field not in self.Bits:
self.Bits[a0_dst_field] = -1
Var = self.Bits[a0_dst_field]
logs.log_info3(
'catchBitWrite side=%s dst=%d (%s) wdata=%s "%s"' %
(Side, a0_dst_field, Dst, abitwdata, Text))
Addr = logs.intx(veri.peek_mem('%s.paddress' % (self.Path), str(1)))
if Side == 'a':
if Addr in self.proga:
Text = self.proga[Addr]
else:
Text = ' a empty'
if Side == 'b':
if Addr in self.progb:
Text = self.progb[Addr]
else:
Text = ' b empty'
Dst = getDst(Text)
a_compare_valid = self.peek('%s_compare_valid' % Side)
if a_compare_valid == 1:
dst_field = self.peek('%s1_dst_field' % Side)
if dst_field > 0:
wdata = self.peek('%s_compare_out' % Side)
Var = self.Bits[dst_field]
logs.log_info3(
'catchBitWrite compare side=%s dst=%d (%s) wdata=%s "%s"'
% (Side, dst_field, Var, wdata, Text))
def catchWrite(self, Side, awaddr, awdata, Addr, Opcode, Ind):
if Side == 'a':
if Addr in self.proga:
Text = self.proga[Addr]
else:
Text = ' a empty'
if Side == 'b':
if Addr in self.progb:
Text = self.progb[Addr]
else:
Text = ' b empty'
Asm = generic_disasm.disasm(Opcode)
Dst = getDst(Text)
Float = logs.binary2float(awdata)
self.Values.append((Dst, Float))
logs.log_info3(
'catchWrite %s side=%s reg=%d wdata=%08x (%f) paddr=%d %08x (%d) %s %s '
% (self.Name, Side, awaddr, awdata, Float, Addr, Opcode, Ind, Text,
Asm))
if Dst != 'empty':
self.simul.checkVar(Dst, Float, awdata)
def mergers(self):
if (self.Golden!=[])and(self.Revised!=[]):
gpx,gpy,gnx,gny = self.Golden.pop(0)
rpx,rpy,rnx,rny = self.Revised.pop(0)
divs = divide((gpx,gpy,gnx,gny),(rpx,rpy,rnx,rny))
logs.log_info3('%d %d %d %d <> %d %d %d %d %s '%(gpx,gpy,gnx,gny,rpx,rpy,rnx,rny,divs))