コード例 #1
0
def monitorResp():
    global respState, data0, data1, data2
    resp_count = logs.peek('tb.resp_count')
    if (resp_count == 0) and (respState == 'idle'):
        veri.force('tb.resp_read', '0')
    else:
        if respState == 'idle':
            veri.force('tb.resp_read', '1')
            veri.force('tb.resp_addr', '0')
            respState = '1'
        elif respState == '1':
            data0 = logs.peek('tb.resp_data')
            veri.force('tb.resp_addr', '1')
            respState = '2'
        elif respState == '2':
            data1 = logs.peek('tb.resp_data')
            veri.force('tb.resp_addr', '2')
            respState = '3'
        elif respState == '3':
            data2 = logs.peek('tb.resp_data')
            respState = '4'
            Msg = data0 | (data1 << 64) | (data2 << 128)
            logs.log_info('resp fifo %x ' % (Msg))
            (Cmd, Tags, Bytes, Addr, Data) = parseMsg(Msg)
            logs.log_info(
                'responce cmd=%s tags=%x bytes=%x addr=%08x data=%x' %
                (cmdKind(Cmd), Tags, Bytes, Addr, Data))
            veri.force('tb.resp_addr', '3')
        elif respState == '4':
            respState = 'idle'
            veri.force('tb.resp_addr', '0')
コード例 #2
0
ファイル: verilog.py プロジェクト: kiranreddi/vlsistuff
def negedge():
    global cycles, idle, Ain, state, Max
    cycles += 1
    veri.force('tb.cycles', str(cycles))
    if (cycles > 1000):
        veri.listing('tb', '1000', 'cucu.list')
        veri.finish()
    rst_n = veri.peek('tb.rst_n')
    if (rst_n != '1'):
        ain = veri.peek('tb.ain')
        Len = len(ain)
        Max = 1 << Len
        return

    veri.force('tb.en', '1')

    if state == 'idle':
        Ain = random.randint(0, Max)
        veri.force('tb.ain', logs.make_str(Ain))
        veri.force('tb.vldin', '1')
        state = 'work0'
    elif state == 'work0':
        veri.force('tb.vldin', '0')
        state = 'wait0'
    elif state == 'wait0':
        vldout = logs.peek('tb.vldout')
        if vldout == 1:
            Out = logs.peek('tb.out')
            Exp = int(math.sqrt(Ain))
            if Out == Exp:
                logs.log_correct('in=%d out=%d' % (Ain, Out))
            else:
                logs.log_wrong('ain=%d max=%d expected=%d act=%d' %
                               (Ain, Max, int(math.sqrt(Ain)), Out))
            state = 'idle'
コード例 #3
0
ファイル: axiClass.py プロジェクト: psumesh/vlsistuff
    def run(self):
        if len(self.queue) > 10:
            veri.force('tb.freak_arready', '0')
        else:
            veri.force('tb.freak_arready', '1')

        freak_arvalid = logs.peek('tb.freak_arvalid')
        if (freak_arvalid == 1) and (len(self.queue) <= 10):
            freak_araddr = logs.peek('tb.freak_araddr')
            freak_arid = logs.peek('tb.freak_arid')
            self.queue.append((freak_araddr, freak_arid))
            logs.log_info(
                'drive arid=%d %x %d araddr=%x len=%d' %
                (freak_arid, freak_arid >> 6, freak_arid & 0x3f, freak_araddr,
                 (len(self.queue) <= 10)))
            monitorIds('drive', freak_arid)

        if self.waiting:
            veri.force('tb.freak_rvalid', '0')
            self.waiting -= 1
            return

        if len(self.queue) == 0: return
        self.waiting = 2
        Pos = my_random.randi(0, len(self.queue) - 1)
        Pos = 0
        (addr, id) = self.queue.pop(Pos)
        veri.force('tb.freak_rvalid', '1')
        veri.force('tb.freak_rid', str(id))
        veri.force('tb.freak_rdata', str(addr))
        logs.log_info('rvalid id=%x %x %d    rdata=%x' %
                      (id, id >> 6, id & 0x3f, addr))
        monitorIds('rsp', id)
コード例 #4
0
def axi_clk():
    axi.run()
    if veri.peek('tb.wvalid') == '1':
        wdata = logs.peek('tb.wdata')
        Expecteds[-1] += int(math.sqrt(wdata))
        wlast = logs.peek('tb.wlast')
        if wlast == 1:
            Expecteds.append(0)
コード例 #5
0
def cucu():
    veri.force('tb.req_addr', '0')
    veri.force('tb.req_data', '0')
    veri.force('tb.req_write', '0')
    veri.force('tb.resp_addr', '0')
    veri.force('tb.resp_read', '0')
    req_count = logs.peek('tb.req_count')
    resp_count = logs.peek('tb.resp_count')
    resp_data = logs.peek('tb.resp_data')
コード例 #6
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
def cucu():
    veri.force('tb.aaa', '0')
    veri.force('tb.bbb', '0')
    veri.force('tb.ccc', '0')
    veri.force('tb.clk0', '0')
    veri.force('tb.clk1', '0')
    veri.force('tb.eee', '0')
    qbad = logs.peek('tb.qbad')
    qgood = logs.peek('tb.qgood')
コード例 #7
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
def cucu():
    veri.force('tb.anglein','0')
    veri.force('tb.nreset','0')
    veri.force('tb.startpulse','0')
    veri.force('tb.vector_mode','1')
    veri.force('tb.xin','0')
    veri.force('tb.yin','0')
    angleout = logs.peek('tb.angleout')
    donepulse = logs.peek('tb.donepulse')
    xout = logs.peek('tb.xout')
    yout = logs.peek('tb.yout')
コード例 #8
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
    def run(self, Area):
        if self.state == 'read':
            md_rvalid = veri.peek('%s.md_rvalid' % self.Path)
            if md_rvalid == '1':
                md_rdata = logs.peek('%s.md_rdata' % self.Path)
                md_rresp = logs.peek('%s.md_rresp' % self.Path)
                md_rid = logs.peek('%s.md_rid' % self.Path)
                logs.log_info(
                    'read addr=0x%x data=0x%x %x %x %s %s' %
                    (self.Addr, md_rdata, md_rresp, md_rid, Area, self.Note))
                self.state = 'idle'
                self.waiting = 100

        if self.waiting > 0:
            self.waiting -= 1
            if (self.waiting < 5) and (self.state == 'read'):
                logs.log_info('read addr=%0x%x didnt end' % (self.Addr))
                self.state = 'idle'
            return
        ext_core_rst_n = veri.peek('%s.ext_core_rst_n' % self.Path)
        veri.force('%s.tl42x_ocem_core_rst_r' % self.Path, ext_core_rst_n)
        if ext_core_rst_n == '0': return

        if self.state == 'idle':
            if self.wrqueue == []: return
            self.Kind, self.Addr, self.Data, self.Note = self.wrqueue.pop(0)
            self.state = 'addr'
            return

        if self.state == 'addr':
            Ok = self.driveAddr(self.Addr, True)
            if Ok: self.state = 'addr1'
        elif self.state == 'addr1':
            self.driveAddr(self.Addr, False)
            self.waiting = 2
            if self.Kind == 'write':
                self.state = 'data'
            else:
                self.state = 'read'
                self.waiting = 100
        elif self.state == 'data':
            Ok = self.driveData(self.Data, True)
            if Ok: self.state = 'after'
        elif self.state == 'after':
            self.driveData(self.Data, False)
            if self.Area:
                Area = self.Area
            logs.log_info('written addr=0x%x data=0x%x %s %s' %
                          (self.Addr, self.Data, Area, self.Note))
            self.state = 'window'
            self.waiting = 100
        elif self.state == 'window':
            self.state = 'idle'
コード例 #9
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
def negedge():
    global cycles, idle, Ain, state, Max, Pause
    cycles += 1
    veri.force('tb.cycles', str(cycles))
    if (cycles > 1000000):
        veri.listing('tb', '1000', 'cucu.list')
        veri.finish()
        return
    veri.force('tb.en', '1')

    rst_n = veri.peek('tb.rst_n')
    if (rst_n != '1') and (cycles < 100):
        ain = veri.peek('tb.ain')
        Len = len(ain)
        Max = 1 << Len
        veri.force('tb.makeStuckList', '1')
        return

    if (cycles > 30):
        for Mon in Monitors:
            Mon.run()

    if state == 'reset':
        Pause -= 1
        if Pause == 0:
            state = 'idle'
            veri.force('tb.rst_n', '1')
    elif state == 'idle':
        Ain = random.randint(0, Max)
        veri.force('tb.ain', logs.make_str(Ain))
        veri.force('tb.vldin', '1')
        state = 'work0'
    elif state == 'work0':
        veri.force('tb.vldin', '0')
        state = 'wait0'
    elif state == 'wait0':
        vldout = logs.peek('tb.vldout')
        if vldout == 1:
            state = 'idle'
            return
            Out = logs.peek('tb.out')
            Exp = int(math.sqrt(Ain))
            if Out == Exp:
                logs.log_correct('in=%d out=%d' % (Ain, Out))
            else:
                logs.log_wrong('ain=%d max=%d expected=%d act=%d' %
                               (Ain, Max, int(math.sqrt(Ain)), Out))
            state = 'idle'
コード例 #10
0
ファイル: lvdsMonitor.py プロジェクト: psumesh/vlsistuff
    def run1(self):
        if veri.peek('tb.dut.dig_top.usat_tx.enable') != '1': return
        cnt = logs.peek('tb.dut.dig_top.usat_tx.serializer.cnt')
        if cnt != 11: return
        din0 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_0')
        din1 = veri.peek('tb.dut.dig_top.usat_tx.serializer.data_in_1')
        Chr0 = encdec_8b10b.trans10to8(din0)
        Chr1 = encdec_8b10b.trans10to8(din1)
        Chr0 = nice(Chr0)
        Chr1 = nice(Chr1)
        self.Stream[0].append(Chr0)
        self.Stream[1].append(Chr1)
        self.dins.append(
            ('%03x' % (logs.intx(din1)), '%03x' % (logs.intx(din0))))
        if len(self.dins) > 8: self.dins.pop(0)
        if len(self.Stream[0]) > 8: self.Stream[0].pop(0)
        if len(self.Stream[1]) > 8: self.Stream[1].pop(0)
        #        if len(self.Stream[0])==8:
        #            logs.log_info('STREAM side0 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))
        #            logs.log_info('STREAM side1 %d %s %s'%(len(self.Stream[0]),self.Stream[0],self.Stream[1]))

        if syncAll(self.Stream[0]) and syncAll(self.Stream[1]):
            self.syncState = 'idle'
        if self.syncState == 'idle':
            if sync8(self.Stream[0]) and sync8(self.Stream[1]):
                self.syncState = 'sync8'
                self.Stream[0] = []
                self.Stream[1] = []
        elif self.syncState == 'sync8':
            if len(self.Stream[0]) == 8:
                logs.log_info('STREAM8   %s %s' %
                              (self.Stream[1], self.Stream[0]))
                #                logs.log_info('STREAM8 X  %s'%str(self.dins))
                self.Stream[0] = []
                self.Stream[1] = []

        txc_0 = logs.peek('tb.dut.dig_top.usat_tx.txc_0')
        txd_0 = logs.peek('tb.dut.dig_top.usat_tx.txd_0')
        txc_1 = logs.peek('tb.dut.dig_top.usat_tx.txc_1')
        txd_1 = logs.peek('tb.dut.dig_top.usat_tx.txd_1')

        #        logs.log_info('side0 %s %s  %s %02x     side1 %s %s    %s %02x'%(din0,Chr0,self.txc_0,self.txd_0,din1,Chr1,self.txc_1,self.txd_1))

        self.txc_0 = txc_0
        self.txd_0 = txd_0
        self.txc_1 = txc_1
        self.txd_1 = txd_1
コード例 #11
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
def monitors():
    for Reg in MONREG:
        Now = logs.peek('tb.generator.%s' % Reg)
        if Reg not in monVals:
            monVals[Reg] = -1
        if monVals[Reg] != Now:
            logs.log_info('register change %s %d -> %d' %
                          (Reg, monVals[Reg], Now))
        monVals[Reg] = Now
コード例 #12
0
ファイル: axiMonitor.py プロジェクト: psumesh/vlsistuff
 def peek(self, Sig):
     Net = Sig
     if Sig in self.Renames:
         Net = self.Renames[Sig]
     if self.Prefix != '':
         Net = '%s%s' % (self.Prefix, Sig)
     if self.Suffix != '':
         Net = '%s%s' % (Sig, self.Suffix)
     return logs.peek('%s%s' % (self.Path, Net))
コード例 #13
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ファイル: axiSlave.py プロジェクト: psumesh/vlsistuff
    def peek(self, Sig):
        Orig = Sig
        if Sig in self.Fixed: return self.Fixed[Sig]
        if self.prefix != '': Sig = '%s%s' % (self.prefix, Sig)
        if self.suffix != '': Sig = '%s%s' % (Sig, self.suffix)
        if Sig in self.Translates:
            Sig = self.Translates[Sig]

        return logs.peek('%s%s' % (self.Path, Sig))
コード例 #14
0
def pclk():
    if veri.peek('tb.pready') == '0':
        veri.force('tb.psel', '0')
        veri.force('tb.penable', '0')
        return
    prdata = logs.peek('tb.prdata')
    veri.force('tb.psel', '1')
    veri.force('tb.penable', '1')
    Exp = Expecteds.pop(0)
    logs.log_info('RESULT %d  exp %d' % (prdata, Exp))
コード例 #15
0
 def peek(self,Sig):
     if Sig in self.noList:
         return 0
     if Sig in self.translations:
         Sig = self.translations[Sig]
     if self.Path=='':
         Full = self.rename(Sig)
     else:
         Full = '%s.%s'%(self.Path,self.rename(Sig))
     return logs.peek(Full)
コード例 #16
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 def evaluateUntil(self, Which):
     if Which == 0:
         Expr, Trans, Timeout = self.wait_until0
     else:
         Expr, Trans, Timeout = self.wait_until1
     Dir = {}
     for _, Rep, Var in Trans:
         X = logs.peek(Var)
         Dir[Rep] = X
     Res = eval(Expr, Dir)
     return Res
コード例 #17
0
def cucu():
    veri.force('tb.paddr', '0')
    veri.force('tb.pclk', '0')
    veri.force('tb.penable', '0')
    veri.force('tb.presetn', '0')
    veri.force('tb.psel', '0')
    veri.force('tb.pstrb', '0')
    veri.force('tb.pwdata', '0')
    veri.force('tb.pwrite', '0')
    key0 = logs.peek('tb.key0')
    key1 = logs.peek('tb.key1')
    limits0 = logs.peek('tb.limits0')
    limits1 = logs.peek('tb.limits1')
    prdata = logs.peek('tb.prdata')
    prdata_wire = logs.peek('tb.prdata_wire')
    pready = logs.peek('tb.pready')
    pslverr = logs.peek('tb.pslverr')
コード例 #18
0
def drive_tx():
    global pauseBetweenTxs
    if pauseBetweenTxs:
        pauseBetweenTxs -= 1
        veri.force('tb.write_tx0', '0')
        return
    tx_empty = logs.peek('tb.tx_empty0')
    if tx_empty == 1:
        fdata = random.randint(0, 255)
        veri.force('tb.txdata0', str(fdata))
        veri.force('tb.write_tx0', '1')
        pauseBetweenTxs = 10
        scoreboard.append(fdata)
    else:
        veri.force('tb.write_tx0', '0')
        pauseBetweenTxs = 10
コード例 #19
0
def negedge():
    global cycles
    cycles += 1
    veri.force('tb.cycles', str(cycles))
    if (cycles > 100000):
        veri.finish()
    rst_n = veri.peek('tb.rst_n')
    if (rst_n != '1'):
        return

    if (cycles == 30):
        veri.listing('tb', '100', 'deep.list')
    if (cycles > 30):
        for Mon in Monitors:
            Mon.run()
        Baud = logs.peek('tb.dut.uart_baudrate')
        uart.baudRate = Baud
コード例 #20
0
ファイル: verilog.py プロジェクト: psumesh/vlsistuff
def monitor_rx():
    global arrivedCharacters
    if veri.peek('tb.rx_valid0')=='1':
        fdata = logs.peek('tb.rxdata0')
        if scoreboard==[]:
            logs.log_wrong('character arrived unexpectedly (%x)'%fdata)
        else:
            Expected = scoreboard.pop(0)
            if Expected==fdata:
                logs.log_correct('character arrived correctly (%x)'%fdata)
            else:
                logs.log_wrong('character arrived uncorrectly exp=%02x    act=%02x '%(Expected,fdata))
                

        arrivedCharacters += 1
        if arrivedCharacters>=TEST_LENGTH:
            logs.finish()
        veri.force('tb.read_rx0','1')
    else:
        veri.force('tb.read_rx0','0')
コード例 #21
0
ファイル: avlMasterClass.py プロジェクト: psumesh/vlsistuff
class avlMasterClass(logs.driverClass):
    def __init__(self, Path, Monitors):
        logs.driverClass.__init__(self, Path, Monitors)
        self.Queue = []

    def run(self):
        if self.waiting > 0:
            self.waiting -= 1
            return
        if self.state == 'write':
            if self.valid('avl_waitrequest'): return
            self.state = 'idle'
            self.force('avl_write', 0)
            self.force('avl_read', 0)
            self.force('avl_writedata', 0)
            self.force('avl_address', 0)
            self.force('avl_byteenable', 0)
            return
        elif self.state == 'read':
            if self.valid('avl_waitrequest'): return
            self.force('avl_write', 0)
            self.force('avl_read', 0)
            self.force('avl_writedata', 0)
            self.force('avl_address', 0)
            self.force('avl_byteenable', 0)
            if self.valid('avl_readdatavalid'):
                self.state = 'idle'
                rdata = self.peek('avl_readdata')
                logs.log_info('reading %08x' % rdata)
            return

        if self.Queue == []: return

        Cmd = self.Queue.pop(0)
        wrds = Cmd.split()
        if wrds[0] == 'write':
            Addr = eval(wrds[1])
            Wdata = eval(wrds[2])
            self.force('avl_write', 1)
            self.force('avl_read', 0)
            self.force('avl_writedata', Wdata)
            self.force('avl_address', Addr)
            self.force('avl_byteenable', 0xffffffff)
            self.state = 'write'
            self.waiting = 1
        elif wrds[0] == 'read':
            Addr = eval(wrds[1])
            self.force('avl_write', 0)
            self.force('avl_read', 1)
            self.force('avl_writedata', 0)
            self.force('avl_address', Addr)
            self.force('avl_byteenable', 0)
            self.state = 'read'
            self.waiting = 1
        elif wrds[0] == 'wait':
            self.waiting = eval(wrds[1])
            return
        elif wrds[0] == 'finish':
            veri.finish()

    avl_readdata = logs.peek('tb.avl_readdata')
    avl_readdatavalid = logs.peek('tb.avl_readdatavalid')
    avl_waitrequest = logs.peek('tb.avl_waitrequest')
コード例 #22
0
ファイル: colorlib.py プロジェクト: psumesh/vlsistuff
 def peek(self, Pin):
     return logs.peek('%s.%s' % (self.Path, Pin))
コード例 #23
0
 def peek(self, Sig):
     return logs.peek('%s.%s%s' % (self.Path, Sig, self.Which))
コード例 #24
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def monitorStuff(Net):
    Val = logs.peek(Net)
    if Val!=0:
        logs.log_error('PANIC activated on %s %s'%(Net,veri.peek(Net)))
        return 1
    return 0
コード例 #25
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def snapshot():
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.panic_d_ids_fifo" % logs.peek("tb.dut.merger0.axi_rd_4_merger.panic_d_ids_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.panic_c_ids_fifo" % logs.peek("tb.dut.merger0.axi_rd_4_merger.panic_c_ids_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.panic_b_ids_fifo" % logs.peek("tb.dut.merger0.axi_rd_4_merger.panic_b_ids_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.panic_a_ids_fifo" % logs.peek("tb.dut.merger0.axi_rd_4_merger.panic_a_ids_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.a_ar_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_rd_4_merger.a_ar_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.a_ar_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_rd_4_merger.a_ar_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.a_ids_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.a_ids_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.a_ids_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.a_ids_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.b_ar_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_rd_4_merger.b_ar_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.b_ar_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_rd_4_merger.b_ar_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.b_ids_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.b_ids_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.b_ids_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.b_ids_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.c_ar_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_rd_4_merger.c_ar_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.c_ar_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_rd_4_merger.c_ar_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.c_ids_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.c_ids_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.c_ids_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.c_ids_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.d_ar_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_rd_4_merger.d_ar_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.d_ar_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_rd_4_merger.d_ar_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.d_ids_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.d_ids_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.d_ids_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_rd_4_merger.d_ids_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.rdata_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_rd_4_merger.rdata_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_rd_4_merger.rdata_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_rd_4_merger.rdata_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_acount" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_acount"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_bcount" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_bcount"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_ccount" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_ccount"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_dcount" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_dcount"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_readout" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_readout"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_d_b_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_d_b_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_d_aw_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_d_aw_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_c_b_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_c_b_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_c_aw_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_c_aw_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_b_out_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_b_out_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_b_b_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_b_b_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_b_aw_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_b_aw_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_a_b_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_a_b_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.panic_a_aw_fifo" % logs.peek("tb.dut.merger0.axi_wr_4_merger.panic_a_aw_fifo"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_aw_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_aw_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_aw_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_aw_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_b_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_b_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_b_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_b_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_win_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_win_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.a_win_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.a_win_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_aw_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_aw_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_aw_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_aw_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_b_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_b_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_b_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_b_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_out_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_out_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_out_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_out_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_win_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_win_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.b_win_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.b_win_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_aw_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_aw_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_aw_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_aw_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_b_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_b_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_b_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_b_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_win_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_win_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.c_win_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.c_win_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_aw_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_aw_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_aw_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_aw_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_b_fifo.panic_overflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_b_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_b_fifo.panic_underflow" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_b_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_win_fifo.panic_in" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_win_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.merger0.axi_wr_4_merger.d_win_fifo.panic_out" % logs.peek("tb.dut.merger0.axi_wr_4_merger.d_win_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.panic_r_fifo" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.panic_r_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.panic_ar_fifo" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.panic_ar_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.a_r_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.a_r_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.a_r_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.a_r_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.ar_fifo.panic_overflow" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.ar_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.ar_fifo.panic_underflow" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.ar_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.b_r_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.b_r_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.b_r_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.b_r_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.c_r_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.c_r_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.c_r_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.c_r_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.d_r_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.d_r_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.d_r_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.d_r_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.r_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.r_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_rd_4_splitter.r_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_rd_4_splitter.r_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.panic_w_fifo" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.panic_w_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.panic_order_fifo" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.panic_order_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.panic_b_fifo" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.panic_b_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.panic_aw_fifo" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.panic_aw_fifo"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.aw_fifo.panic_overflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.aw_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.aw_fifo.panic_underflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.aw_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.b_fifo.panic_overflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.b_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.b_fifo.panic_underflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.b_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_a_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_a_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_a_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_a_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_b_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_b_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_b_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_b_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_c_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_c_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_c_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_c_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_d_fifo.panic_in" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_d_fifo.panic_in"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.back_bid_d_fifo.panic_out" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.back_bid_d_fifo.panic_out"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.order_fifo.panic_overflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.order_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.order_fifo.panic_underflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.order_fifo.panic_underflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.w_fifo.panic_overflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.w_fifo.panic_overflow"))
    logs.log_info("SNP %x  tb.dut.splitter0.axi_wr_4_splitter.w_fifo.panic_underflow" % logs.peek("tb.dut.splitter0.axi_wr_4_splitter.w_fifo.panic_underflow"))
コード例 #26
0
 def peek(self,Sig):
     return logs.peek('%s.%s'%(self.Path,Sig))
コード例 #27
0
ファイル: verilog.py プロジェクト: greenblat/sv2v
def cucu():
    veri.force('tb.apu_master_flags_i', '0')
    veri.force('tb.apu_master_gnt_i', '0')
    veri.force('tb.apu_master_result_i', '0')
    veri.force('tb.apu_master_valid_i', '0')
    veri.force('tb.boot_addr_i', '0')
    veri.force('tb.clk_i', '0')
    veri.force('tb.clock_en_i', '0')
    veri.force('tb.cluster_id_i', '0')
    veri.force('tb.core_id_i', '0')
    veri.force('tb.data_err_i', '0')
    veri.force('tb.data_gnt_i', '0')
    veri.force('tb.data_rdata_i', '0')
    veri.force('tb.data_rvalid_i', '0')
    veri.force('tb.debug_addr_i', '0')
    veri.force('tb.debug_halt_i', '0')
    veri.force('tb.debug_req_i', '0')
    veri.force('tb.debug_resume_i', '0')
    veri.force('tb.debug_wdata_i', '0')
    veri.force('tb.debug_we_i', '0')
    veri.force('tb.ext_perf_counters_i', '0')
    veri.force('tb.fetch_enable_i', '0')
    veri.force('tb.instr_gnt_i', '0')
    veri.force('tb.instr_rdata_i', '0')
    veri.force('tb.instr_rvalid_i', '0')
    veri.force('tb.irq_i', '0')
    veri.force('tb.irq_id_i', '0')
    veri.force('tb.irq_sec_i', '0')
    veri.force('tb.rst_ni', '0')
    veri.force('tb.test_en_i', '0')
    apu_master_flags_o = logs.peek('tb.apu_master_flags_o')
    apu_master_op_o = logs.peek('tb.apu_master_op_o')
    apu_master_operands_o = logs.peek('tb.apu_master_operands_o')
    apu_master_ready_o = logs.peek('tb.apu_master_ready_o')
    apu_master_req_o = logs.peek('tb.apu_master_req_o')
    apu_master_type_o = logs.peek('tb.apu_master_type_o')
    core_busy_o = logs.peek('tb.core_busy_o')
    data_addr_o = logs.peek('tb.data_addr_o')
    data_be_o = logs.peek('tb.data_be_o')
    data_req_o = logs.peek('tb.data_req_o')
    data_wdata_o = logs.peek('tb.data_wdata_o')
    data_we_o = logs.peek('tb.data_we_o')
    debug_gnt_o = logs.peek('tb.debug_gnt_o')
    debug_halted_o = logs.peek('tb.debug_halted_o')
    debug_rdata_o = logs.peek('tb.debug_rdata_o')
    debug_rvalid_o = logs.peek('tb.debug_rvalid_o')
    instr_addr_o = logs.peek('tb.instr_addr_o')
    instr_req_o = logs.peek('tb.instr_req_o')
    irq_ack_o = logs.peek('tb.irq_ack_o')
    irq_id_o = logs.peek('tb.irq_id_o')
    sec_lvl_o = logs.peek('tb.sec_lvl_o')
コード例 #28
0
def cucu():
    veri.force('tb.arready', '0')
    veri.force('tb.awready', '0')
    veri.force('tb.bid', '0')
    veri.force('tb.bresp', '0')
    veri.force('tb.bvalid', '0')
    veri.force('tb.rdata', '0')
    veri.force('tb.rid', '0')
    veri.force('tb.rlast', '0')
    veri.force('tb.rresp', '0')
    veri.force('tb.rvalid', '0')
    veri.force('tb.rxd', '0')
    veri.force('tb.wready', '0')
    araddr = logs.peek('tb.araddr')
    arburst = logs.peek('tb.arburst')
    arid = logs.peek('tb.arid')
    arlen = logs.peek('tb.arlen')
    arsize = logs.peek('tb.arsize')
    arvalid = logs.peek('tb.arvalid')
    awaddr = logs.peek('tb.awaddr')
    awburst = logs.peek('tb.awburst')
    awid = logs.peek('tb.awid')
    awlen = logs.peek('tb.awlen')
    awsize = logs.peek('tb.awsize')
    awvalid = logs.peek('tb.awvalid')
    bready = logs.peek('tb.bready')
    rready = logs.peek('tb.rready')
    txd = logs.peek('tb.txd')
    wdata = logs.peek('tb.wdata')
    wlast = logs.peek('tb.wlast')
    wstrb = logs.peek('tb.wstrb')
    wvalid = logs.peek('tb.wvalid')
コード例 #29
0
 def peek(self,Sig):
     Full = '%s.%s'%(self.Path,Sig)
     return logs.peek(Full)
コード例 #30
0
 def peek(self, Sig):
     if self.Path == '':
         Full = self.rename(Sig)
     else:
         Full = '%s.%s' % (self.Path, self.rename(Sig))
     return logs.peek(Full)