cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
cfg_file.close()
# create a traffic generator, and point it to the file we just created
system.tgen = TrafficGen(config_file = cfg_file_name)
# add a communication monitor
system.monitor = CommMonitor()
# connect the traffic generator to the bus via a communication monitor
system.tgen.port = system.monitor.slave
system.monitor.master = system.membus.slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
# every period, dump and reset all stats
periodicStatDump(period)
# run Forrest, run!
root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate(nxt_state * period)
print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
(burst_size, nbr_banks, max_stride)
system.l2cache = L2Cache(size='512kB', writeback_clean=True)
system.l2cache.xbar = L2XBar()
system.l1cache.mem_side = system.l2cache.xbar.slave
system.l2cache.cpu_side = system.l2cache.xbar.master
# make the L3 mostly exclusive, and correspondingly ensure that the L2
# writes back also clean lines to the L3
system.l3cache = L3Cache(size='4MB', clusivity='mostly_excl')
system.l3cache.xbar = L2XBar()
system.l2cache.mem_side = system.l3cache.xbar.slave
system.l3cache.cpu_side = system.l3cache.xbar.master
system.l3cache.mem_side = system.membus.slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
# every period, dump and reset all stats
periodicStatDump(period)
# run Forrest, run!
root = Root(full_system=False, system=system)
root.system.mem_mode = 'timing'
m5.instantiate()
m5.simulate(nxt_state * period)
# print all we need to make sense of the stats output
print "lat_mem_rd with %d iterations, ranges:" % iterations
for r in ranges:
print r
if len(bm) == 2:
ethz_print_msg("Error! not implemented")
elif len(bm) == 1:
root = Root(full_system=True, system=test_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
if options.timesync:
root.time_sync_enable = True
if options.frame_capture:
VncServer.frame_capture = True
if (GEM5_PERIODIC_STATS_DUMP == "TRUE"):
periodicStatDump(GEM5_PERIODIC_STATS_DUMP_PERIOD)
# This is to make bare_metal simulation work with ARMv8. If we don't make these
# modifications, ARMv8 does not boot in bare_metal mode
if (options.bare_metal):
test_sys.boot_loader = options.kernel
test_sys.gic_cpu_addr = 0x00000001 # Dummy
test_sys.flags_addr = 0x00000001 # Dummy
test_sys.realview.nvmem = SimpleMemory(range=AddrRange(0, size='1MB'))
test_sys.realview.nvmem.port = test_sys.membus.master
ethz_perform_sanity_checks(test_sys, options)
# test_sys.pim_sys.cpu.commitWidth=1
# test_sys.pim_sys.cpu.decodeWidth=1
# test_sys.pim_sys.cpu.dispatchWidth=1
