def memory_bandwidth_parser(cls, flags, param):
# The string will be in tick/byte
# Convert to byte/tick
value = 1.0 / float(param)
# Convert to byte/s
value = ticks.fromSeconds(value)
return cls('%fB/s' % value)
def memory_bandwidth_parser(cls, flags, param):
# The string will be in tick/byte
# Convert to byte/tick
value = 1.0 / float(param)
# Convert to byte/s
value = ticks.fromSeconds(value)
return cls('%fB/s' % value)
def _create_random_traffic(
self,
duration: str,
rate: str,
block_size: int,
min_addr: int,
max_addr: int,
rd_perc: int,
data_limit: int,
) -> None:
"""
This function yields (creates) a random traffic based on the input
params. Then it will yield (create) an exit traffic (exit traffic is
used to exit the simulation).
:param duration: The number of ticks for the generator core to generate
traffic.
:param rate: The rate at which the synthetic data is read/written.
:param block_size: The number of bytes to be read/written with each
request.
:param min_addr: The lower bound of the address range the generator
will read/write from/to.
:param max_addr: The upper bound of the address range the generator
will read/write from/to.
:param rd_perc: The percentage of read requests among all the generated
requests. The write percentage would be equal to 100 - rd_perc.
:param data_limit: The amount of data in bytes to read/write by the
generator before stopping generation.
"""
duration = fromSeconds(toLatency(duration))
rate = toMemoryBandwidth(rate)
period = fromSeconds(block_size / rate)
min_period = period
max_period = period
yield self.generator.createRandom(
duration,
min_addr,
max_addr,
block_size,
min_period,
max_period,
rd_perc,
data_limit,
)
yield self.generator.createExit(0)
def _create_traffic(self) -> Iterator[BaseTrafficGen]:
"""
A python generator that yields (creates) a linear traffic with the
specified params in the generator core and then yields (creates) an
exit traffic.
:rtype: Iterator[BaseTrafficGen]
"""
duration = fromSeconds(toLatency(self._duration))
rate = toMemoryBandwidth(self._rate)
period = fromSeconds(self._block_size / rate)
min_period = period
max_period = period
yield self.generator.createLinear(
duration,
self._min_addr,
self._max_addr,
self._block_size,
min_period,
max_period,
self._rd_perc,
self._data_limit,
)
yield self.generator.createExit(0)
def runSim(sim_time):
""" Run the simulation.
This will run the simulation ignoring exits for "Max Insts", but
raising an exception for all other exit types.
@param sim_time the amount of guest-time to simulate as a string
(e.g., "10ms")
"""
ticks = fromSeconds(toLatency(sim_time))
abs_ticks = m5.curTick() + ticks
exit_event = m5.simulate(ticks)
while exit_event.getCause() != "simulate() limit reached":
# It's possible (likely) there are a few max insts exit events still
# scheduled. We should ignore these. See fastforward
print "Exited:", exit_event.getCause()
if not exit_event.getCause().startswith("Max Insts"):
raise UnexpectedExit(exit_event.getCause())
exit_event = m5.simulate(abs_ticks - m5.curTick())
def scheduleRecordedEvents(eventq, controller, logFile, events=['all'], scalingFactor=1.0, tickOffset=m5.curTick()):
'''Schedule recorded events.
This function's `logFile', `events' and `options' parameters are the same
as those of the timeAccuratePlaybackDevice() and simplePlaybackDevice()
functions. The `options' parameter is read from `controller'.getOptions().
The function schedules recorded events into the given eventqueue `eventq'.
No event is run in this function, only inserted into the event queue. All
events are scheduled relative to `tickOffset'. By default the recorded
delay times are converted to the appropriate number of simulator ticks and
events inserted at the respective point in (tick) time. To speed up or slow
down the playback the delay is multiplied by `scalingFactor'.
'''
import m5.event
from m5 import ticks
class PlaybackEvent(m5.event.Event):
def __init__(self, event, machine):
super(PlaybackEvent, self).__init__()
self.event = event
self.machine = machine
def __call__(self):
self.modifyMachine()
def modifyMachine(self):
if controller.machine:
controller.accessMachine(lambda c,m: (self.swapMachine(c), c.stateModified(self.event)))
else:
# Machine not yet created...
self.swapMachine(controller)
def swapMachine(self, controller):
controller.machine = self.machine
debug.pp(PARTREF, 'Scheduling recorded events from {0}'.format(logFile))
pbDev = RawPlaybackDevice(openLogFile(logFile), events, controller.getOptions())
for (timespan, event, machine) in pbDev:
when = tickOffset + ticks.fromSeconds(timespan)*scalingFactor
debug.pp(PARTREF, 'schedule event <{0}, {1}>'.format(event, when))
eventq.schedule(PlaybackEvent(event, machine), int(when))
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.ticks import fixGlobalFrequency, fromSeconds
root = LinuxArmFSSystem(mem_mode='atomic_noncaching',
machine_type='VExpress_GEM5_V1',
mem_class=SimpleMemory,
cpu_class=ArmV8KvmCPU,
num_cpus=2).create_root()
fixGlobalFrequency()
root.sim_quantum = fromSeconds(m5.util.convert.anyToLatency("1ms"))