def sim_register(self, value_store, state_store):
"""
Adapted from Brennan's SB_DFF simulation in mantle
"""
cur_clock = value_store.get_value(self.clk)
if not state_store:
state_store['prev_clock'] = cur_clock
print(init)
state_store['cur_val'] = BitVector(
init, num_bits=N) if N is not None else bool(init)
# if has_reset:
# cur_reset = value_store.get_value(self.rst)
# if s:
# cur_s = value_store.get_value(self.S)
prev_clock = state_store['prev_clock']
# if not n:
# clock_edge = cur_clock and not prev_clock
# else:
# clock_edge = not cur_clock and prev_clock
clock_edge = cur_clock and not prev_clock
new_val = state_store['cur_val'].as_bool_list(
) if N is not None else state_store['cur_val']
if clock_edge:
input_val = value_store.get_value(getattr(self, "in"))
enable = True
if has_ce:
enable = value_store.get_value(self.en)
if enable:
# if r and sy and cur_r:
# new_val = False
# elif s and sy and cur_s:
# new_val = True
# else:
# new_val = input_val
new_val = input_val
# if has_reset and not cur_reset: # Reset is asserted low
# if N is not None:
# new_val = [False for _ in range(N)]
# else:
# new_val = None
# if s and not sy and cur_s:
# new_val = True
state_store['prev_clock'] = cur_clock
state_store['cur_val'] = BitVector(
new_val, num_bits=N) if N is not None else new_val
value_store.set_value(self.out, new_val)
def simulate(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0), signed=signed)
in1 = BitVector(value_store.get_value(self.in1), signed=signed)
out = python_op(in0, in1).as_bool_list()
if out_type is Bit:
assert len(
out
) == 1, "out_type is Bit but the operation returned a list of length {}".format(
len(out))
out = out[0]
value_store.set_value(self.out, out)
def test_romb():
main = DefineCircuit("test_romb",
"RDATAOUT", Out(Bits(8)),
"CLK", In(Clock)) # FIXME: hack
romb = ROMB(512, 8, [0b00000001, 0b11111111] + [0] * 510)
wire(romb.RADDR, uint(1, 9))
wire(romb.RCLK, main.CLK)
wire(romb.RE, 1)
wire(romb.RDATA, main.RDATAOUT)
EndCircuit()
sim = PythonSimulator(main, clock=main.CLK)
sim.evaluate()
sim.advance(2)
assert BitVector(sim.get_value(main.RDATAOUT)) == BitVector(0b11111111, num_bits=8)
def sim_mem(self, value_store, state_store):
cur_clk = value_store.get_value(self.clk)
if not state_store:
state_store['mem'] = [BitVector(0, width) for _ in range(depth)]
state_store['prev_clk'] = cur_clk
prev_clk = state_store['prev_clk']
clk_edge = cur_clk and not prev_clk
rdata = value_store.get_value(self.rdata)
if clk_edge:
index = BitVector(value_store.get_value(self.raddr)).as_int()
rdata = state_store['mem'][index].as_bool_list()
if clk_edge:
if value_store.get_value(self.wen):
index = BitVector(value_store.get_value(self.waddr)).as_int()
state_store['mem'][index] = BitVector(
value_store.get_value(self.wdata))
state_store['prev_clk'] = cur_clk
value_store.set_value(self.rdata, rdata)
def test_ramb():
main = DefineCircuit("test_ramb",
"RDATA", Out(Bits(8)),
"WDATA", In(Bits(8)),
"WE", In(Bit),
"CLK", In(Clock))
ramb = RAMB(512, 8, [0b00000001, 0b11111111] + [0] * 510)
wire(ramb.RADDR, uint(1, 9))
wire(ramb.RCLK, main.CLK)
wire(ramb.RE, 1)
wire(ramb.WADDR, uint(1, 9))
wire(ramb.WCLK, main.CLK)
wire(ramb.WE, main.WE)
wire(ramb.RDATA, main.RDATA)
wire(ramb.WDATA, main.WDATA)
EndCircuit()
sim = PythonSimulator(main, clock=main.CLK)
sim.set_value(main.WE, False)
sim.evaluate()
sim.advance(2)
assert BitVector(sim.get_value(main.RDATA)) == BitVector(0b11111111, num_bits=8)
# Write 0xBE to WADDR = 1
sim.set_value(main.WE, True)
sim.set_value(main.WDATA, BitVector(0xBE, num_bits=8))
sim.advance(2)
# Read RADDR = 1 again
sim.set_value(main.WE, False)
sim.evaluate()
sim.advance(2)
assert BitVector(sim.get_value(main.RDATA)) == BitVector(0xBE, num_bits=8)
def sim_register(self, value_store, state_store):
"""
Adapted from Brennan's SB_DFF simulation in mantle
"""
cur_clock = value_store.get_value(self.clk)
if not state_store:
state_store['prev_clock'] = cur_clock
state_store['cur_val'] = BitVector(
init, num_bits=N) if N is not None else bool(init)
if has_reset:
cur_reset = value_store.get_value(self.arst)
# if s:
# cur_s = value_store.get_value(self.S)
prev_clock = state_store['prev_clock']
# if not n:
# clock_edge = cur_clock and not prev_clock
# else:
# clock_edge = not cur_clock and prev_clock
clock_edge = cur_clock and not prev_clock
new_val = state_store['cur_val'].as_bool_list(
) if N is not None else state_store['cur_val']
if clock_edge:
new_val = value_store.get_value(self.I)
if has_reset and cur_reset:
new_val = BitVector(init,
num_bits=N) if N is not None else bool(init)
# if s and not sy and cur_s:
# new_val = True
state_store['prev_clock'] = cur_clock
state_store['cur_val'] = BitVector(
new_val, num_bits=N) if N is not None else new_val
value_store.set_value(self.O, new_val)
def testvectors(circuit, func, input_ranges=None, mode='complete'):
check(circuit, func)
args = []
for i, (name, port) in enumerate(circuit.interface.ports.items()):
if port.isoutput():
if isinstance(port, BitType):
args.append([BitVector(0),BitVector(1)])
elif isinstance(port, ArrayType):
num_bits = type(port).N
if isinstance(port, SIntType):
if input_ranges is None:
start = -2**(num_bits - 1)
end = 2**(num_bits - 1) # We don't subtract one because range end is exclusive
input_range = range(start, end)
else:
input_range = input_ranges[i]
args.append([BitVector(x, num_bits=num_bits, signed=True) for x in input_range])
else:
if input_ranges is None:
input_range = range(1<<num_bits)
else:
input_range = input_ranges[i]
args.append([BitVector(x, num_bits=num_bits) for x in input_range])
else:
assert True, "can't test Tuples"
nargs = len(args)
tests = []
for test in product(*args):
test = list(test)
result = func(*test)
if isinstance(result, tuple):
test.extend(result)
else:
test.append(result)
tests.append(test)
return tests
def clb(a, b, c, d):
return (a & b) | (~c & d)
T = UInt(16)
class Combinational(Circuit):
name = "Combinational"
IO = ["a", In(T), "b", In(T), "c", Out(T)]
@classmethod
def definition(io):
wire(clb(io.a, io.b, io.a, io.b), io.c)
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(Combinational)
a = BitVector(148, num_bits=16)
b = BitVector(41, num_bits=16)
simulator.set_value(Combinational.a, a)
simulator.set_value(Combinational.b, b)
simulator.evaluate()
assert simulator.get_value(Combinational.c) == clb(a, b, a, b)
print("Success!")
class Combinational(m.Circuit):
name = "Combinational"
IO = ["a", m.In(T), "b", m.In(T), "c", m.Out(T)]
@classmethod
def definition(io):
m.wire(clb(io.a, io.b, io.a, io.b), io.c)
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(Combinational)
a = BitVector(148, num_bits=16)
b = BitVector(41, num_bits=16)
simulator.set_value(Combinational.a, a)
simulator.set_value(Combinational.b, b)
simulator.evaluate()
assert BitVector(simulator.get_value(Combinational.c)) == clb(a, b, a, b)
print("Success!")
# In[4]:
m.compile("build/Combinational", Combinational, output="coreir")
get_ipython().magic('cat build/Combinational.json')
def simulate(self, value_store, state_store):
in_ = BitVector(value_store.get_value(getattr(self, "in")))
out = reduce(python_op, in_)
value_store.set_value(self.out, out)
def simulate(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0))
in1 = BitVector(value_store.get_value(self.in1))
out = python_op(in0, in1).as_bool_list()[0]
value_store.set_value(self.out, out)
def simulate(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0))
in1 = BitVector(value_store.get_value(self.in1))
out = python_op(in0, in1).as_bool_list()
# print(f"{python_op}({in0}, {in1}), {out}")
value_store.set_value(self.out, out)
def simulate_coreir_add(self, value_store, state_store):
I0 = BitVector(value_store.get_value(self.I0), width)
I1 = BitVector(value_store.get_value(self.I1), width)
value_store.set_value(self.O, I0 + I1)
def simulate(self, value_store, state_store):
I0 = BitVector(value_store.get_value(self.I0))
I1 = BitVector(value_store.get_value(self.I1))
O = python_op(I0, I1).as_bool_list()[0]
value_store.set_value(self.O, O)
def simulate_bits_invert(self, value_store, state_store):
_in = BitVector(value_store.get_value(self.I))
O = (~_in).as_bool_list()
value_store.set_value(self.O, O)
m.wire(io.I, getattr(regs[0], "in"))
m.fold(regs, foldargs={"in":"out"})
m.wire(regs[-1].out, io.O)
# In[2]:
from magma.backend.verilog import compile as compile_verilog
print(compile_verilog(ShiftRegister))
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(ShiftRegister, clock=ShiftRegister.CLK)
outputs = []
for i in range(0, 1 << N):
simulator.set_value(ShiftRegister.I, BitVector(i, N))
for j in range(2):
simulator.step()
simulator.evaluate()
O = simulator.get_value(ShiftRegister.O)
outputs.append(BitVector(O))
print([val.as_int() for val in outputs])
adder2 = FullAdder()
wire(io.a[1], adder2.a)
wire(io.b[1], adder2.b)
wire(adder1.cout, adder2.cin)
adder3 = FullAdder()
wire(io.a[2], adder3.a)
wire(io.b[2], adder3.b)
wire(adder2.cout, adder3.cin)
adder4 = FullAdder()
wire(io.a[3], adder4.a)
wire(io.b[3], adder4.b)
wire(adder3.cout, adder4.cin)
wire(adder4.cout, io.cout)
wire(bits([adder1.out, adder2.out, adder3.out, adder4.out]), io.out)
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(Adder4)
simulator.set_value(Adder4.a, BitVector(2, num_bits=4))
simulator.set_value(Adder4.b, BitVector(3, num_bits=4))
simulator.set_value(Adder4.cin, True)
simulator.evaluate()
assert simulator.get_value(Adder4.out) == BitVector(6, num_bits=4)
assert simulator.get_value(Adder4.cout) == False
print("Success!")
def simulate_coreir_add(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0), width)
in1 = BitVector(value_store.get_value(self.in1), width)
value_store.set_value(self.out, in0 + in1)
# In[2]:
from magma.backend.verilog import compile as compile_verilog
print(compile_verilog(ResetShiftRegister))
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(ResetShiftRegister, clock=ResetShiftRegister.CLK)
outputs = []
simulator.set_value(ResetShiftRegister.reset, True)
for i in range(0, 1 << N):
simulator.set_value(ResetShiftRegister.I, BitVector(i, N))
for j in range(2):
if i == 9:
if j == 0:
simulator.set_value(ResetShiftRegister.reset, False)
else:
simulator.set_value(ResetShiftRegister.reset, True)
simulator.step()
simulator.evaluate()
O = simulator.get_value(ResetShiftRegister.O)
outputs.append(BitVector(O).as_int())
print(outputs)
def simulate(self, value_store, state_store):
I0 = BitVector(value_store.get_value(self.I0))
I1 = BitVector(value_store.get_value(self.I1))
O = (I0 << I1).as_bool_list()
value_store.set_value(self.O, O)
@classmethod
def definition(io):
adders = [FullAdder() for _ in range(N)]
circ = m.braid(adders, foldargs={"cin": "cout"})
m.wire(io.a, circ.a)
m.wire(io.b, circ.b)
m.wire(io.cin, circ.cin)
m.wire(io.cout, circ.cout)
m.wire(io.out, circ.out)
return Adder
if __name__ == "__main__":
from magma.python_simulator import PythonSimulator
from magma.scope import Scope
from magma.bit_vector import BitVector
Adder4 = DefineAdder(4)
simulator = PythonSimulator(Adder4)
scope = Scope()
simulator.set_value(Adder4.a, scope,
BitVector(2, num_bits=4).as_bool_list())
simulator.set_value(Adder4.b, scope,
BitVector(3, num_bits=4).as_bool_list())
simulator.set_value(Adder4.cin, scope, True)
simulator.evaluate()
assert simulator.get_value(Adder4.out, scope) == int2seq(6, 4)
assert simulator.get_value(Adder4.cout, scope) == False
print("Success!")
def simulate(self, value_store, state_store):
in_ = BitVector(value_store.get_value(self.I))
O = reduce(python_op, in_)
value_store.set_value(self.O, O)
def simulate(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0))
in1 = BitVector(value_store.get_value(self.in1))
sel = BitVector(value_store.get_value(self.sel))
out = in1 if sel.as_int() else in0
value_store.set_value(self.out, out)
# coding: utf-8
# In[1]:
from magma import *
class Combinational(Circuit):
name = "Combinational"
IO = ["x", In(UInt(16)), "y", In(UInt(16)), "z", Out(UInt(16))]
@classmethod
def definition(io):
wire(io.x + io.y, io.z)
# In[2]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(Combinational)
simulator.set_value(Combinational.x, BitVector(76, num_bits=16))
simulator.set_value(Combinational.y, BitVector(43, num_bits=16))
simulator.evaluate()
assert simulator.get_value(Combinational.z) == BitVector(76 + 43, num_bits=16)
print("Success!")
def simulate_bits_invert(self, value_store, state_store):
_in = BitVector(value_store.get_value(getattr(self, "in")))
out = (~_in).as_bool_list()
value_store.set_value(self.out, out)
def simulate(self, value_store, state_store):
I0 = BitVector(value_store.get_value(self.I0))
I1 = BitVector(value_store.get_value(self.I1))
S = BitVector(value_store.get_value(self.S))
O = I1 if S.as_int() else in0
value_store.set_value(self.O, O)
def simulate(self, value_store, state_store):
in0 = BitVector(value_store.get_value(self.in0))
in1 = BitVector(value_store.get_value(self.in1))
out = (in0 << in1).as_bool_list()
value_store.set_value(self.out, out)
def simulate(self, value_store, state_store):
sel = BitVector(value_store.get_value(self.I.sel))
out = BitVector(value_store.get_value(self.I.data[sel.as_int]))
value_store.set_value(self.O, out)
def simulate(self, value_store, state_store):
I0 = BitVector(value_store.get_value(self.I0))
I1 = BitVector(value_store.get_value(self.I1))
O = python_op(I0, I1).as_bool_list()
# print(f"{python_op}({I0}, {I1}), {out}")
value_store.set_value(self.O, O)
one_hot_mux([is_op0, is_op1, is_op2, is_op3],
[op0_out, op1_out, op2_out, op3_out]))
# In[2]:
m.compile("build/SimpleALU", SimpleALU, output="coreir")
get_ipython().magic('cat build/SimpleALU.json')
# In[3]:
from magma.simulator import PythonSimulator
from magma.bit_vector import BitVector
simulator = PythonSimulator(SimpleALU)
simulator.set_value(SimpleALU.a, BitVector(3, num_bits=4))
simulator.set_value(SimpleALU.b, BitVector(2, num_bits=4))
simulator.set_value(SimpleALU.opcode, BitVector(0, num_bits=2))
simulator.evaluate()
assert BitVector(simulator.get_value(SimpleALU.out)) == BitVector(
3 + 2, num_bits=4), simulator.get_value(SimpleALU.out)
simulator.set_value(SimpleALU.a, BitVector(3, num_bits=4))
simulator.set_value(SimpleALU.b, BitVector(2, num_bits=4))
simulator.set_value(SimpleALU.opcode, BitVector(1, num_bits=2))
simulator.evaluate()
assert BitVector(simulator.get_value(SimpleALU.out)) == BitVector(3 - 2,
num_bits=4)
simulator.set_value(SimpleALU.a, BitVector(3, num_bits=4))
simulator.set_value(SimpleALU.b, BitVector(2, num_bits=4))
simulator.set_value(SimpleALU.opcode, BitVector(2, num_bits=2))
