def _process_port(port):
scope = Scope()
if isinstance(port, PortWrapper):
port = port.select_path
if isinstance(port, SelectPath):
for i in port[1:-1]:
scope = Scope(parent=scope, instance=i.instance)
port = port[-1]
return port, scope
def process_port(self, port):
scope = Scope()
if isinstance(port, fault.actions.Peek):
port = port.port
if isinstance(port, PortWrapper):
port = port.select_path
if isinstance(port, SelectPath):
for i in port[1:-1]:
scope = Scope(parent=scope, instance=i.instance)
port = port[-1]
return port, scope
def test_up_parallel():
width = 5
numOut = 2
testVal = 3
scope = Scope()
inType = Array[width, In(BitIn)]
outType = Array[numOut, Out(inType)]
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
upParallel = UpsampleParallel(numOut, inType)
wire(upParallel.I, testcircuit.I)
wire(testcircuit.O, upParallel.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.I, int2seq(testVal, width), scope)
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
for i in range(numOut):
assert seq2int(sim.get_value(testcircuit.O[i], scope)) == testVal
def test_two_coreir_muxes():
width = 2
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
inType = Array(width, In(BitIn))
outType = Array(width, Out(Bit))
args = ['I', inType, 'S', In(Bit), 'O', outType] + ClockInterface(
False, False)
testcircuit = DefineCircuit('test_partition', *args)
coreir_mux = DefineCoreirMux(None)()
coreir_mux(testcircuit.I[0], testcircuit.I[1], testcircuit.S)
wire(coreir_mux.out, testcircuit.O[0])
cmux = CommonlibMuxN(cirb, 2, 1)
wire(cmux.I.data[0][0], testcircuit.I[0])
wire(cmux.I.data[1][0], testcircuit.I[1])
wire(cmux.I.sel[0], testcircuit.S)
wire(cmux.out[0], testcircuit.O[1])
EndCircuit()
sim = CoreIRSimulator(
testcircuit,
testcircuit.CLK,
context=c,
namespaces=["commonlib", "mantle", "coreir", "global"])
def test_deserializer():
width = 11
numIn = 13
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
inType = In(Array(width, Bit))
outType = Out(Array(numIn, Array(width, BitIn)))
args = ['I', inType, 'O', outType, 'valid',
Out(Bit)] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Deserializer', *args)
deserializer = Deserializer(cirb, inType, numIn)
wire(deserializer.I, testcircuit.I)
wire(testcircuit.O, deserializer.out)
wire(testcircuit.valid, deserializer.valid)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=cirb.context,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(numIn):
sim.set_value(testcircuit.I, int2seq(i, width), scope)
assert sim.get_value(testcircuit.valid, scope) == (i == numIn - 1)
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
assert sim.get_value(testcircuit.valid, scope) == False
def test_1dlb_flicker_ce_with_2_stride():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineOneDimensionalLineBuffer(cirb, Array[8, In(Bit)], 1, 2,
8, 2, 0, True)
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(50):
if i % 2 == 0:
sim.set_value(testcircuit.I[0], int2seq(1, 8), scope)
sim.set_value(testcircuit.CE, 1, scope)
else:
sim.set_value(testcircuit.I[0], int2seq(2, 8), scope)
sim.set_value(testcircuit.CE, 0, scope)
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
print([
seq2int(sim.get_value(testcircuit.O[0][r], scope))
for r in range(2)
])
print(sim.get_value(testcircuit.valid, scope))
# for some reason, lb going to 0 when flickering valid on and off for ce
for r in range(2):
assert (sim.get_value(testcircuit.valid, scope) == 0
or seq2int(sim.get_value(testcircuit.O[0][r], scope)) != 0)
def test_shift_s():
num_in = 4
test_vals = [2, 5, 3, 8]
shift_amount = 2
in_type = ST_SSeq(num_in, ST_Int())
scope = Scope()
args = ['I', In(in_type.magma_repr()), 'O',
Out(in_type.magma_repr())] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
rshift = DefineShift_S(num_in, shift_amount, in_type.t)()
wire(rshift.I, testcircuit.I)
wire(testcircuit.O, rshift.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
for i, val in enumerate(test_vals):
sim.set_value(testcircuit.I[i], int2seq(val, 8), scope)
sim.evaluate()
for i, val in enumerate(test_vals[shift_amount:]):
assert seq2int(sim.get_value(
testcircuit.O[i + shift_amount])) == test_vals[i]
def test_db_flicker_ce():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineDelayedBuffer(cirb, Array[8, Bit], 4, 1, 16, 1)
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(100000):
if i % 2 == 0 and i > 20:
sim.set_value(testcircuit.I[0], int2seq(1, 8), scope)
sim.set_value(testcircuit.CE, 1, scope)
else:
sim.set_value(testcircuit.I[0], int2seq(2, 8), scope)
sim.set_value(testcircuit.CE, 0, scope)
if i % 2 == 0 and i > 20: #(not i % 16 == 0 or i == 0):
sim.set_value(testcircuit.WE, 1, scope)
else:
sim.set_value(testcircuit.WE, 0, scope)
sim.evaluate()
print(seq2int(sim.get_value(testcircuit.O[0], scope)))
print(sim.get_value(testcircuit.valid, scope))
# for some reason, lb going to 0 when flickering valid on and off for ce
assert (sim.get_value(testcircuit.valid, scope) == 0
or seq2int(sim.get_value(testcircuit.O[0], scope)) != 0)
sim.advance_cycle()
def test_ram_flicker_we():
scope = Scope()
c = coreir.Context()
cirb = CoreIRBackend(c)
testcircuit = DefineRAM(8, 1)
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=c,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
sim.set_value(testcircuit.WADDR[0], 0, scope)
sim.set_value(testcircuit.RADDR[0], 0, scope)
sim.set_value(testcircuit.WDATA[0], 1, scope)
for i in range(20):
sim.set_value(testcircuit.WE, 0, scope)
sim.evaluate()
sim.advance_cycle()
sim.set_value(testcircuit.WE, 1, scope)
sim.evaluate()
sim.advance_cycle()
sim.set_value(testcircuit.WE, 0, scope)
sim.evaluate()
sim.advance_cycle()
print(sim.get_value(testcircuit.RDATA, scope))
def test_sseqTupleCreator():
width = 8
scope = Scope()
testvals = [1, 2]
T = ST_TSeq(2, 0, ST_Int())
T_magma = T.magma_repr()
args = ['I0',
In(T_magma), 'I1',
In(T_magma), 'O',
Out(Array[2, T_magma])] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
sseqTupleCreator = SSeqTupleCreator(T)
wire(testcircuit.I0, sseqTupleCreator.I0)
wire(testcircuit.I1, sseqTupleCreator.I1)
wire(testcircuit.O, sseqTupleCreator.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.I0, int2seq(testvals[0], width), scope)
sim.set_value(testcircuit.I1, int2seq(testvals[1], width), scope)
sim.evaluate()
for i in range(len(testvals)):
assert seq2int(sim.get_value(testcircuit.O[i], scope)) == testvals[i]
def test_atomTupleCreator():
width = 8
scope = Scope()
T0 = ST_Int()
T1 = ST_Bit()
T_outer_output = ST_Atom_Tuple(T0, T1)
args = ['I0', In(T0.magma_repr()), 'I1', In(T1.magma_repr()), \
'O', Out(T_outer_output.magma_repr())] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
atomTupleAppender = AtomTupleCreator(T0, T1)
wire(testcircuit.I0, atomTupleAppender.I0)
wire(testcircuit.I1, atomTupleAppender.I1)
wire(testcircuit.O, atomTupleAppender.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.I0, int2seq(4, width), scope)
sim.set_value(testcircuit.I1, True, scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O[0], scope)) == 4
assert sim.get_value(testcircuit.O[1], scope) == True
def test_sseqTupleAppender():
width = 8
scope = Scope()
testvals = [1, 2, 3]
T_inner = ST_TSeq(2, 0, ST_Int())
T_outer_input = ST_SSeq_Tuple(2, ST_Int())
T_outer_output = ST_SSeq_Tuple(3, ST_Int())
args = ['I0', In(T_outer_input.magma_repr()), 'I1', In(T_inner.magma_repr()), \
'O', Out(T_outer_output.magma_repr())] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test', *args)
sseqTupleAppender = SSeqTupleAppender(T_inner, 2)
wire(testcircuit.I0, sseqTupleAppender.I0)
wire(testcircuit.I1, sseqTupleAppender.I1)
wire(testcircuit.O, sseqTupleAppender.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.I0[0], int2seq(testvals[0], width), scope)
sim.set_value(testcircuit.I0[1], int2seq(testvals[1], width), scope)
sim.set_value(testcircuit.I1, int2seq(testvals[2], width), scope)
sim.evaluate()
for i in range(len(testvals)):
assert seq2int(sim.get_value(testcircuit.O[i], scope)) == testvals[i]
def test_reduce_parallel():
width = 11
numIn = 13
scope = Scope()
inType = In(Array[numIn, Array[width, BitIn]])
outType = Out(Array[width, Bit])
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Reduce_Parallel', *args)
reducePar = ReduceParallel(numIn, DefineAdd(width))
wire(reducePar.I, testcircuit.I)
wire(testcircuit.O, reducePar.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(numIn):
sim.set_value(testcircuit.I[i], int2seq(i, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O, scope)) == sum(range(numIn))
def test_up_sequential():
width = 5
numOut = 2
testVal = 3
c = coreir.Context()
scope = Scope()
inType = Array(width, In(BitIn))
outType = Out(inType)
args = ['I', inType, 'O', outType, 'READY',
Out(Bit)] + ClockInterface(False, False)
testcircuit = DefineCircuit('TestUpSequential', *args)
coreir_backend = CoreIRBackend(c)
upSequential = UpsampleSequential(coreir_backend, numOut, inType)
wire(upSequential.I, testcircuit.I)
wire(testcircuit.O, upSequential.O)
wire(testcircuit.READY, upSequential.READY)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=coreir_backend.context)
sim.set_value(testcircuit.I, int2seq(testVal, width), scope)
sim.evaluate()
for i in range(numOut):
assert seq2int(sim.get_value(testcircuit.O, scope)) == testVal
sim.advance_cycle()
sim.evaluate()
assert sim.get_value(testcircuit.READY, scope) == (i == numOut - 1)
def test_delayed_buffer_parallel():
scope = Scope()
testcircuit = DefineDelayedBuffer(Array[8, Bit], 4, 2, 16)
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.CE, True, scope)
last_output = 2
last_input = 2
# do two cycles
for clock_index in range(32):
# for each cycle, input every other of first half
if clock_index % 16 < 4 and clock_index % 2 == 0:
sim.set_value(testcircuit.WE, True, scope)
sim.set_value(testcircuit.I[0], int2seq(last_input, 8), scope)
sim.set_value(testcircuit.I[1], int2seq(last_input + 1, 8), scope)
last_input += 2
else:
sim.set_value(testcircuit.WE, False, scope)
sim.evaluate()
if clock_index % 4 == 0:
assert sim.get_value(testcircuit.valid, scope) == True
assert seq2int(sim.get_value(testcircuit.O, scope)[0]) == last_output
last_output += 1
else:
assert sim.get_value(testcircuit.valid, scope) == False
sim.advance_cycle()
sim.evaluate()
def create_dict_recurse(circ, cur_scope, values):
scope_dict = {}
values[cur_scope.value()] = scope_dict
scope_dict['_instances'] = []
scope_dict['_top'] = {}
scope_dict['_top']['inputs'] = {}
scope_dict['_top']['outputs'] = {}
for name, bit in circ.interface.ports.items():
if bit.isoutput():
scope_dict['_top']['inputs'][name] = []
else:
scope_dict['_top']['outputs'][name] = []
for inst in circ.instances:
scope_dict['_instances'].append(get_inst_name(inst))
scope_dict[get_inst_name(inst)] = {}
scope_dict[get_inst_name(inst)]['inputs'] = {}
scope_dict[get_inst_name(inst)]['outputs'] = {}
for name, bit in inst.interface.ports.items():
if bit.isinput():
scope_dict[get_inst_name(inst)]['inputs'][name] = []
else:
scope_dict[get_inst_name(inst)]['outputs'][name] = []
if not isprimitive(inst):
create_dict_recurse(type(inst),
Scope(instance=inst, parent=cur_scope), values)
def test_downsample_parallel_non_zero_idx():
width = 5
numIn = 4
scope = Scope()
outType = Array[width, Out(BitIn)]
inType = Array[numIn, In(outType)]
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Downsample_Parallel', *args)
downsampleParallel = DownsampleParallel(numIn, 2, inType.T)
wire(downsampleParallel.I, testcircuit.I)
wire(testcircuit.O, downsampleParallel.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(numIn):
sim.set_value(testcircuit.I[i], int2seq(i, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O, scope)) == 2
def test_downsample_parallel():
width = 5
numIn = 2
testVal = 3
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
outType = Array(width, Out(BitIn))
inType = Array(numIn, In(outType))
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Downsample_Parallel', *args)
downsampleParallel = DownsampleParallel(cirb, numIn, inType.T)
wire(downsampleParallel.I, testcircuit.I)
wire(testcircuit.O, downsampleParallel.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=cirb.context,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(numIn):
sim.set_value(testcircuit.I[i], int2seq(testVal, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O, scope)) == testVal
def test_reduce_parallel():
width = 11
numIn = 13
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
inType = In(Array(numIn, Array(width, BitIn)))
outType = Out(Array(width, Bit))
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Reduce_Parallel', *args)
reducePar = ReduceParallel(cirb, numIn,
renameCircuitForReduce(DefineAdd(width)))
coreirConst = DefineCoreirConst(width, 0)()
wire(reducePar.I.data, testcircuit.I)
wire(reducePar.I.identity, coreirConst.out)
wire(testcircuit.O, reducePar.out)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=cirb.context,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for i in range(numIn):
sim.set_value(testcircuit.I[i], int2seq(i, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O, scope)) == sum(range(numIn))
def test_simulator_tuple():
width = 8
testValInt = 80
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
inDims = [2, width]
tupleEl = Array[inDims[1], Bit]
nestedTuples = Array[inDims[0], Tuple(sel=tupleEl, data=tupleEl)]
tupleValues = {'sel':int2seq(testValInt, width), 'data':int2seq(testValInt+20, width)}
inType = In(nestedTuples)
outType = Out(Array[2*inDims[0], tupleEl])
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('test_simulator_tuple', *args)
wire(testcircuit.I[0].data, testcircuit.O[0])
wire(testcircuit.I[0].sel, testcircuit.O[1])
wire(testcircuit.I[1].data, testcircuit.O[2])
wire(testcircuit.I[1].sel, testcircuit.O[3])
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK, context=cirb.context,
namespaces=["aetherlinglib", "commonlib", "mantle", "coreir", "global"])
sim.set_value(testcircuit.I, [tupleValues, tupleValues], scope)
getArrayInTuple = sim.get_value(testcircuit.I[0].data, scope)
getTuples = sim.get_value(testcircuit.I, scope)
assert getArrayInTuple == tupleValues['data']
assert getTuples[0] == tupleValues
assert getTuples[1] == tupleValues
def test_partition():
width = 8
parallelism = 2
testValInt = 210
testValBits = int2seq(testValInt)
scope = Scope()
inType = Array[width, In(BitIn)]
outType = Array[parallelism, Out(Bit)]
args = ['I', inType, 'O', outType] + ClockInterface(False, False)
testcircuit = DefineCircuit('test_partition', *args)
part = Partition(inType, parallelism)
wire(part.I, testcircuit.I)
wire(testcircuit.O, part.O)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
sim.set_value(testcircuit.I, int2seq(testValInt, width), scope)
sim.evaluate()
for i in range(int(width / parallelism)):
assert seq2int(sim.get_value(testcircuit.O, scope)) == \
seq2int(testValBits[i*parallelism:(i+1)*parallelism])
sim.advance_cycle()
sim.evaluate()
def test_serializer_multi_clock_elements():
width = 5
num_in = 3
time_per_element = 2
num_iterations = 2
scope = Scope()
inType = In(Array[num_in, Array[width, BitIn]])
outType = Out(Array[width, Bit])
args = ['I', inType, 'O', outType, 'ready_up', Out(Bit), 'valid_up', In(Bit), 'ready_down', In(Bit),
'valid_down', Out(Bit)] + ClockInterface(True, False)
testcircuit = DefineCircuit('TestUpSequential', *args)
serializer = Serializer(num_in, time_per_element, inType.T, has_ce=True)
wire(serializer.I, testcircuit.I)
wire(testcircuit.O, serializer.O)
wire(testcircuit.ready_up, serializer.ready_up)
wire(testcircuit.valid_up, serializer.valid_up)
wire(testcircuit.ready_down, serializer.ready_down)
wire(testcircuit.valid_down, serializer.valid_down)
wire(testcircuit.CE, serializer.CE)
EndCircuit()
sim = CoreIRSimulator(testcircuit, testcircuit.CLK)
sim.set_value(testcircuit.valid_up, True, scope)
sim.set_value(testcircuit.ready_down, True, scope)
sim.set_value(testcircuit.CE, True, scope)
for i in range(num_iterations):
parts_of_elements_emitted = 0
elements_emitted = 0
clk = -1
while elements_emitted < num_in:
clk += 1
if elements_emitted == 0:
for j in range(num_in):
# note: parts_of_elements_emitted only ever 0 or 1 here as this code only executes if
# elements_emitted == 0
sim.set_value(testcircuit.I[j], int2seq(i * (num_in + time_per_element) + \
j * time_per_element + parts_of_elements_emitted, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O, scope)) == i * (num_in + time_per_element) + \
elements_emitted * time_per_element + (parts_of_elements_emitted % time_per_element)
# valid_down and ready_up should always be true since valid_up, ready_down, and CE always true
assert sim.get_value(testcircuit.valid_down, scope) == True
if elements_emitted == 0:
assert sim.get_value(testcircuit.ready_up, scope) == True
else:
assert sim.get_value(testcircuit.ready_up, scope) == False
sim.advance_cycle()
sim.evaluate()
# since ready, valid, and CE in always true, always increment elements counters
parts_of_elements_emitted += 1
if parts_of_elements_emitted % time_per_element == 0:
elements_emitted += 1
def test_partial_parallel_2_convolution():
from .partialParallel2Convolution import partialParallel2Convolution
scope = Scope()
sim = CoreIRSimulator(partialParallel2Convolution,
partialParallel2Convolution.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
sim.set_value(partialParallel2Convolution.valid_data_in, 1, scope)
sim.set_value(partialParallel2Convolution.ready_data_out, 1, scope)
sim.set_value(partialParallel2Convolution.CE, 1, scope)
# these check the outputs, as there is a delay between feeding inputs in and getting the results back
cur_row_to_check = 0
cur_col_to_check = 0
successfully_checked_all_valid_outputs = False
for row in range(num_rows + 3):
for col in range(0, num_cols, 2):
# a necessary adjustment as running tests for multiple clocks after inputting full image
# to get rest of the outputs
if row < num_rows:
sim.set_value(partialParallel2Convolution.I0,
int2seq(image_matrix[row][col], int_width))
sim.set_value(partialParallel2Convolution.I1,
int2seq(image_matrix[row][col + 1], int_width))
sim.evaluate()
assert sim.get_value(partialParallel2Convolution.ready_data_in,
scope) == 1
if sim.get_value(partialParallel2Convolution.valid_data_out,
scope) == 1:
if cur_row_to_check in valid_rows and cur_col_to_check in valid_cols:
if seq2int(
sim.get_value(partialParallel2Convolution.O0,
scope)
) != results[cur_row_to_check][cur_col_to_check]:
print(cur_col_to_check)
assert seq2int(
sim.get_value(partialParallel2Convolution.O0, scope)
) == results[cur_row_to_check][cur_col_to_check]
if cur_col_to_check + 1 in valid_cols:
assert seq2int(
sim.get_value(partialParallel2Convolution.O1,
scope)) == results[cur_row_to_check][
cur_col_to_check + 1]
if not cur_row_to_check in valid_rows:
successfully_checked_all_valid_outputs = True
break
cur_col_to_check += 2
cur_col_to_check = cur_col_to_check % num_cols
if cur_col_to_check == 0:
cur_row_to_check += 1
cur_row_to_check = cur_row_to_check % num_rows
sim.advance_cycle()
if successfully_checked_all_valid_outputs:
break
assert successfully_checked_all_valid_outputs
def test_downsample_stencil_1_per_32():
from .downsampleStencilChain1Per32 import downsampleStencilChain1Per32
scope = Scope()
sim = CoreIRSimulator(downsampleStencilChain1Per32,
downsampleStencilChain1Per32.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
sim.set_value(downsampleStencilChain1Per32.valid_data_in, 1, scope)
sim.set_value(downsampleStencilChain1Per32.ready_data_out, 1, scope)
sim.set_value(downsampleStencilChain1Per32.CE, 1, scope)
# these check the outputs, as there is a delay between feeding inputs in and getting the results back
cur_row_to_check = 0
cur_col_to_check = 0
successfully_checked_all_valid_outputs = False
for row in range(num_rows + 6):
for col in range(0, num_cols, 2):
# a necessary adjustment as running tests for multiple clocks after inputting full image
# to get rest of the outputs
if row < num_rows:
sim.set_value(downsampleStencilChain1Per32.I0,
int2seq(image_matrix[row][col], int_width))
sim.set_value(downsampleStencilChain1Per32.I1,
int2seq(image_matrix[row][col + 1], int_width))
sim.evaluate()
assert sim.get_value(downsampleStencilChain1Per32.ready_data_in,
scope) == 1
if sim.get_value(downsampleStencilChain1Per32.valid_data_out,
scope) == 1:
if cur_row_to_check in valid_out_rows and cur_col_to_check in valid_out_cols:
if seq2int(
sim.get_value(downsampleStencilChain1Per32.O0,
scope)
) != thirdResults[cur_row_to_check][cur_col_to_check]:
print(cur_col_to_check)
print("Overall row and col : ({}, {})".format(row, col))
assert seq2int(
sim.get_value(downsampleStencilChain1Per32.O0, scope)
) == thirdResults[cur_row_to_check][cur_col_to_check]
cur_col_to_check += 1
cur_col_to_check = cur_col_to_check % num_valid_out_cols
if cur_col_to_check == 0:
cur_row_to_check += 1
cur_row_to_check = cur_row_to_check
if not cur_row_to_check in valid_out_rows:
successfully_checked_all_valid_outputs = True
break
sim.advance_cycle()
if successfully_checked_all_valid_outputs:
break
assert successfully_checked_all_valid_outputs
def test_pop_count():
PopCount8 = DefinePopCount(8)
m.compile('build/popcount8', PopCount8, output="coreir")
assert check_files_equal(__file__,
"build/popcount8.json", "gold/popcount8.json")
scope = Scope()
sim = CoreIRSimulator(PopCount8, None)
for I, expected_O in [(1, 1), (2, 1), (3, 2)]:
sim.set_value(PopCount8.I, BitVector[8](I), scope)
sim.evaluate()
assert BitVector[8](sim.get_value(PopCount8.O, scope)).as_int() == expected_O
def run_test_updown_npxPerClock(pxPerClock):
upsampleAmount = 7
c = coreir.Context()
cirb = CoreIRBackend(c)
scope = Scope()
args = ClockInterface(False, False) + RAMInterface(imgSrc, True, True,
pxPerClock)
testcircuit = DefineCircuit(
'Test_UpsampleDownsample_{}PxPerClock'.format(pxPerClock), *args)
imgData = loadImage(imgSrc, pxPerClock)
pixelType = Array(imgData.bitsPerPixel, Bit)
bitsToPixelHydrate = MapParallel(cirb, pxPerClock,
Hydrate(cirb, pixelType))
upParallel = MapParallel(cirb, pxPerClock,
UpsampleParallel(upsampleAmount, pixelType))
downParallel = MapParallel(
cirb, pxPerClock, DownsampleParallel(cirb, upsampleAmount, pixelType))
pixelToBitsDehydrate = MapParallel(cirb, pxPerClock,
Dehydrate(cirb, pixelType))
# Note: input image RAM will send data to hydrate,
# which converts it to form upsample and downsample can use
# note that these do wiriring to connect the RAMs to edge of test circuit and
# adjacent node inside circuit
InputImageRAM(cirb, testcircuit, bitsToPixelHydrate.I, imgSrc, pxPerClock)
OutputImageRAM(cirb, testcircuit, pixelToBitsDehydrate.out,
testcircuit.input_ren, imgSrc, pxPerClock)
wire(upParallel.I, bitsToPixelHydrate.out)
wire(upParallel.O, downParallel.I)
wire(downParallel.O, pixelToBitsDehydrate.I)
EndCircuit()
#GetCoreIRModule(cirb, testcircuit).save_to_file("updown_out{}.json".format(pxPerClock))
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
context=cirb.context,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
LoadImageRAMForSimulation(sim, testcircuit, scope, imgSrc, pxPerClock)
# run the simulation for all the rows
for i in range(imgData.numRows):
sim.evaluate()
sim.advance_cycle()
sim.evaluate()
DumpImageRAMForSimulation(sim, testcircuit, scope, imgSrc, pxPerClock,
validIfEqual)
def test_downsample_sequential_ce_and_rv_always_true():
width = 5
num_elements = 6
active_idx = 3
time_per_element = 1
scope = Scope()
out_type = Array[width, Out(BitIn)]
in_type = In(out_type)
args = [
'I', in_type, 'O', out_type, 'ready_up',
Out(Bit), 'valid_up',
In(Bit), 'ready_down',
In(Bit), 'valid_down',
Out(Bit)
] + ClockInterface(has_ce=True)
testcircuit = DefineCircuit('Test_Downsample_Sequential', *args)
downsampleSequential = DownsampleSequential(num_elements,
time_per_element,
active_idx,
in_type,
has_ce=True)
wire(downsampleSequential.I, testcircuit.I)
wire(testcircuit.O, downsampleSequential.O)
wire(testcircuit.ready_up, downsampleSequential.ready_up)
wire(testcircuit.valid_up, downsampleSequential.valid_up)
wire(testcircuit.ready_down, downsampleSequential.ready_down)
wire(testcircuit.valid_down, downsampleSequential.valid_down)
wire(testcircuit.CE, downsampleSequential.CE)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for clk in range(num_elements):
sim.set_value(testcircuit.valid_up, True, scope)
sim.set_value(testcircuit.ready_down, True, scope)
sim.set_value(testcircuit.CE, True, scope)
sim.set_value(testcircuit.I, int2seq(clk, width), scope)
sim.evaluate()
if clk == active_idx:
assert seq2int(sim.get_value(testcircuit.O, scope)) == clk
assert sim.get_value(testcircuit.valid_down,
scope) == (active_idx == clk // time_per_element)
assert sim.get_value(testcircuit.ready_up, scope) == True
sim.advance_cycle()
sim.evaluate()
def impl_test_1D_line_buffer(magma_type, pixels_per_clock: int,
window_width: int, image_size: int,
output_stride: int, origin: int):
"""Run tests for the 1D line buffer with given token type (magma_type)
and parameters."""
scope = Scope()
# Test line buffer for each combination of parameters and test data.
for in_arrays in generate_test_data_sets_1D(magma_type, pixels_per_clock,
image_size):
a_1D_line_buffer_test(scope, in_arrays, magma_type, pixels_per_clock,
window_width, image_size, output_stride, origin)
def test_downsample_parallel_rv():
width = 5
num_in_per_clk = 4
num_clocks = 5
scope = Scope()
outType = Array[width, Out(BitIn)]
inType = Array[num_in_per_clk, In(outType)]
args = [
'I', inType, 'O', outType, 'ready_up',
Out(Bit), 'valid_up',
In(Bit), 'ready_down',
In(Bit), 'valid_down',
Out(Bit)
] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Downsample_Parallel', *args)
downsampleParallel = DownsampleParallel(num_in_per_clk,
2,
inType.T,
has_ready_valid=True)
wire(downsampleParallel.I, testcircuit.I)
wire(testcircuit.O, downsampleParallel.O)
wire(testcircuit.ready_up, downsampleParallel.ready_up)
wire(testcircuit.valid_up, downsampleParallel.valid_up)
wire(testcircuit.ready_down, downsampleParallel.ready_down)
wire(testcircuit.valid_down, downsampleParallel.valid_down)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
for clk in range(num_clocks):
sim.set_value(testcircuit.valid_up, clk % 4 == 0, scope)
sim.set_value(testcircuit.ready_down, clk % 2 == 0, scope)
for i in range(num_in_per_clk):
sim.set_value(testcircuit.I[i],
int2seq(i + clk * num_in_per_clk, width), scope)
sim.evaluate()
assert seq2int(sim.get_value(testcircuit.O,
scope)) == 2 + clk * num_in_per_clk
assert sim.get_value(testcircuit.valid_down, scope) == (clk % 4 == 0)
assert sim.get_value(testcircuit.ready_up, scope) == (clk % 2 == 0)
sim.advance_cycle()
sim.evaluate()
def test_reduce_partially_parallel():
width = 11
numIn = 12
parallelism = 3
scope = Scope()
inType = In(Array[width, BitIn])
outType = Out(Array[width, Bit])
args = [
'I', Array[parallelism, inType], 'O', outType, 'ready',
Out(Bit), 'valid',
Out(Bit)
] + ClockInterface(False, False)
testcircuit = DefineCircuit('Test_Reduce_Parallel', *args)
reduce_op = ReducePartiallyParallel(numIn, parallelism, DefineAdd(width))
wire(reduce_op.I, testcircuit.I)
wire(testcircuit.O, reduce_op.O)
wire(testcircuit.ready, reduce_op.ready)
wire(testcircuit.valid, reduce_op.valid)
EndCircuit()
sim = CoreIRSimulator(testcircuit,
testcircuit.CLK,
namespaces=[
"aetherlinglib", "commonlib", "mantle", "coreir",
"global"
])
reduce_result = 0
for i in range(numIn * 2 // parallelism):
reduce_result += i + i * 5 + i * 10
sim.set_value(testcircuit.I[0], int2seq(i, width), scope)
sim.set_value(testcircuit.I[1], int2seq(i * 5, width), scope)
sim.set_value(testcircuit.I[2], int2seq(i * 10, width), scope)
sim.evaluate()
# exit last time of loop without going to next iteration, time to check results then
if i % (numIn // parallelism) == (numIn // parallelism) - 1:
assert seq2int(sim.get_value(testcircuit.O,
scope)) == reduce_result
assert sim.get_value(testcircuit.ready, scope) == True
assert sim.get_value(testcircuit.valid, scope) == True
reduce_result = 0
else:
assert sim.get_value(testcircuit.ready, scope) == True
assert sim.get_value(testcircuit.valid, scope) == False
sim.advance_cycle()
sim.evaluate()
