def __init__(self, peak_generator): pe = peak_generator(hwtypes.BitVector.get_family()) assert issubclass(pe, peak.Peak) pe = pe.__call__ (self.__instr_name, self.__instr_type) = pe._peak_isa_ self.__inputs = pe._peak_inputs_ self.__outputs = pe._peak_outputs_ circuit = peak_generator(magma.get_family()) self.__asm, disasm, self.__instr_width, layout = \ peak.auto_assembler.generate_assembler(self.__instr_type) instr_magma_type = type(circuit.interface.ports[self.__instr_name]) self.__circuit = peak.wrap_with_disassembler(circuit, disasm, self.__instr_width, HashableDict(layout), instr_magma_type)
def test_register(): Reg = gen_register2(m.get_family(), m.Bits[2], 1) tester = fault.Tester(Reg, Reg.CLK) tester.circuit.CLK = 0 tester.circuit.ASYNCRESET = 0 tester.eval() tester.circuit.ASYNCRESET = 1 tester.eval() tester.circuit.ASYNCRESET = 0 tester.eval() tester.circuit.value = 0 tester.circuit.en = 0 tester.step(2) tester.circuit.O.expect(1) tester.circuit.value = 2 tester.circuit.en = 1 tester.step(2) tester.circuit.O.expect(2) tester.circuit.en = 0 tester.circuit.value = 3 tester.step(2) tester.circuit.O.expect(2) tester.compile_and_run("verilator")
def get_family(cls): import magma as m return m.get_family()
def get_family(self): import magma as m return m.get_family()
from lassen.sim import gen_pe import magma as m PE = gen_pe(m.get_family()) m.compile(f"examples/build/PE", PE, output="coreir-verilog")