def definition(io):
Is = [io.I[i] for i in range(n)]
muxes = map_(Mux(2), n)
for i in range(n):
shifti = i - k
I = bits([Is[i], Is[shifti] if shifti >= 0 else io.SI])
muxes[i]( I, io.S )
for i in range(n):
Is[i] = muxes[i].O
wire(bits(Is), io.O)
def definition(io):
dffs = m.braid(m.map_(DefineDFF(width, pipe_depth, retime_status),
array_size_1),
joinargs=["data_in", "data_out"],
forkargs=["clk", "en", "reset"])
m.wire(dffs.data_in, io.data_in)
m.wire(dffs.data_out, io.data_out)
m.wire(dffs.clk, io.clk)
m.wire(dffs.en, io.en)
m.wire(dffs.reset, io.reset)
def definition(io):
Is = [io.I[i] for i in range(n)]
muxes = map_(Mux2, n)
for i in range(n):
if op == 'rol':
shifti = (i - k + n) % n
I = bits([Is[i], Is[shifti]])
elif op == 'ror':
shifti = (i + k) % n
I = bits([Is[i], Is[shifti]])
else:
assert False
muxes[i](I, io.S)
for i in range(n):
Is[i] = muxes[i].O
wire(bits(Is), io.O)
def definition(io):
Is = [io.I[i] for i in range(n)]
muxes = map_(Mux2, n)
for i in range(n):
if op == 'lsl':
shifti = i - k
I = bits([Is[i], Is[shifti] if shifti >= 0 else io.SI])
elif op == 'lsr' or op == 'asr':
shifti = i + k
I = bits([Is[i], Is[shifti] if shifti < n else io.SI])
else:
assert False
muxes[i](I, io.S)
for i in range(n):
Is[i] = muxes[i].O
wire(bits(Is), io.O)
def test_str_repr_anon():
And2 = m.DeclareCircuit('And2', "I0", m.In(m.Bit), "I1", m.In(m.Bit), "O",
m.Out(m.Bit))
circ = m.DefineCircuit("Test", "I0", m.In(m.Bits[3]), "I1",
m.In(m.Bits[3]), "O", m.Out(m.Bits[3]))
anon = m.join(m.map_(And2, 3))
m.wire(circ.I0, anon.I0)
m.wire(circ.I1, anon.I1)
m.wire(circ.O, anon.O)
m.EndCircuit()
string = str(anon)
assert string[:len("AnonymousCircuitInst")] == "AnonymousCircuitInst"
assert string[-len(
"<I0: Array[3, In(Bit)], I1: Array[3, In(Bit)], O: Array[3, Out(Bit)]>"
):] == "<I0: Array[3, In(Bit)], I1: Array[3, In(Bit)], O: Array[3, Out(Bit)]>"
assert repr(
anon
) == 'AnonymousCircuitType("I0", array([And2_inst0.I0, And2_inst1.I0, And2_inst2.I0]), "I1", array([And2_inst0.I1, And2_inst1.I1, And2_inst2.I1]), "O", array([And2_inst0.O, And2_inst1.O, And2_inst2.O]))'
def definition(io):
s = flat(join(map_(Swap, n // 2 - 1)), flatargs=['I', 'O'])
wire(io.I[0], io.O[0])
wire(s(io.I[1:-1]), io.O[1:-1])
wire(io.I[-1], io.O[-1])
def definition(io):
s = flat(join(map_(Swap, n // 2)), flatargs=['I', 'O'])
wire(s(io.I), io.O)
def logic(a: m.Bits[10]) -> m.Bits[10]:
return m.join(m.map_(Not, 10))(a)