def test_coreir_wrap(T):
def define_wrap(type_, type_name, in_type):
def sim_wrap(self, value_store, state_store):
input_val = value_store.get_value(getattr(self, "in"))
value_store.set_value(self.out, input_val)
return DeclareCircuit(
f'coreir_wrap{type_name}',
"in", In(in_type), "out", Out(type_),
coreir_genargs = {"type": type_},
coreir_name="wrap",
coreir_lib="coreir",
simulate=sim_wrap
)
foo = DefineCircuit("foo", "r", In(T))
EndCircuit()
top = DefineCircuit("top", "O", Out(Bit))
foo_inst = foo()
wrap = define_wrap(T, "Bit", Bit)()
wire(bit(0), wrap.interface.ports["in"])
wire(wrap.out, foo_inst.r)
wire(bit(0), top.O)
EndCircuit()
with tempfile.TemporaryDirectory() as tempdir:
filename = f"{tempdir}/top"
compile(filename, top, output="coreir")
got = open(f"{filename}.json").read()
expected_filename = f"tests/test_type/test_coreir_wrap_golden_{T}.json"
expected = open(expected_filename).read()
assert got == expected
def DefineMain(self):
arrays = {}
# form arrays
for p in self.pins:
if p.used:
# find names of the form %s[%d]
# these are considered arrays
match = re.findall('(.*)\[(\d+)\]', p.name)
if match:
name, i = match[0]
i = int(i)
# keep track of the indices
if name in arrays:
arrays[name].append(i)
else:
arrays[name] = [i]
# collect top level module arguments
args = []
for p in self.pins:
if p.used:
match = re.findall('(.*)\[(\d+)\]', p.name)
if match:
name, i = match[0]
assert name in arrays
if len(arrays[name]) == 1:
p.rename(name)
args.append(name)
args.append(
In(Bit) if p.direction == INPUT else Out(Bit))
else:
i = int(i)
if i == max(arrays[name]):
args.append(name)
T = Bits[i + 1]
args.append(
In(T) if p.direction == INPUT else Out(T))
else:
args.append(p.name)
if p.name == 'CLKIN':
assert p.direction == INPUT
args.append(In(Clock))
else:
args.append(
In(Bit) if p.direction == INPUT else Out(Bit))
D = DefineCircuit('main', *args, __magma_no_cache__=True)
D.fpga = self
for p in self.peripherals:
if p.used:
#print(p)
p.setup(D)
return D
def test_const_wire(T, t):
foo = DefineCircuit("foo", "I", In(T))
EndCircuit()
top = DefineCircuit("top", "O", Out(Bit))
foo_inst = foo()
wire(t(0), foo_inst.I)
wire(bit(0), top.O)
EndCircuit()
with tempfile.TemporaryDirectory() as tempdir:
filename = f"{tempdir}/top"
compile(filename, top, output="coreir")
got = open(f"{filename}.json").read()
expected_filename = f"tests/test_type/test_const_wire_golden.json"
expected = open(expected_filename).read()
assert got == expected
def Define3to2Op():
Op = DefineCircuit("Op", "I0", In(Bit), "I1", In(Bit), "I2", In(Bit), "O", Out(Bit))
a = And(2)(Op.I0, Op.I1)
b = And(2)(Op.I1, Op.I2)
c = And(2)(Op.I2, Op.I0)
d = Or(3)(a, b, c)
wire(d, Op.O)
EndDefine()
return Op
def test_print_ir():
And2 = DeclareCircuit('And2', "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
AndN2 = DefineCircuit("AndN2", "I", In(Array[2, Bit]), "O", Out(Bit) )
and2 = And2()
wire( AndN2.I[0], and2.I0 )
wire( AndN2.I[1], and2.I1 )
wire( and2.O, AndN2.O )
EndCircuit()
main = DefineCircuit("main", "I0", In(Bit), "I1", In(Bit), "O", Out(Bit))
and2 = AndN2()
main.O( and2(array([main.I0, main.I1])) )
EndCircuit()
result = compile(main)
#print(result)
assert result == """\
def test_fdce():
main = DefineCircuit('main', 'I', In(Bit), "O", Out(Bit), "CLK", In(Clock))
dff = FDCE()
wire(m.enable(1), dff.CE)
wire(0, dff.CLR)
wire(main.I, dff.D)
wire(dff.Q, main.O)
EndCircuit()
print(compile(main))
print(repr(main))
def Decode(i, n, invert=False, **kwargs):
"""
Decode the n-bit number i.
@return: 1 if the n-bit input equals i
"""
assert n <= 8
if os.environ["MANTLE"] == "coreir":
from mantle import eq
from magma import Bits, In, Bit, DefineCircuit, EndDefine, wire, bits, Out
circ = DefineCircuit(f"Decode{i}{n}", "I", In(Bits(n)), "O", Out(Bit))
wire(circ.O, eq(circ.I, bits(i, n)))
EndDefine()
return circ()
i = 1 << i
if invert:
m = 1 << n
mask = (1 << m) - 1
i = mask & (~i)
return uncurry(LUT(i, n, **kwargs))
from magma import DefineCircuit, EndCircuit, In, Out, Bit, Clock
__all__ = ['DFF', 'FF']
_DFF = DefineCircuit('DFF', "D", In(Bit), "CLK", In(Clock), "Q", Out(Bit))
_DFF.verilog = '''\
always @(posedge CLK) begin
Q <= D;
end'''
EndCircuit()
def DFF(init=0, has_ce=False, has_reset=False, has_set=False):
ff = _DFF()
#args = ['I', ff.D, 'CLK', ff.CLK]
#if has_ce:
# args += ['CE', ff.E]
#if has_reset:
# args += ['RESET', ff.R]
#if has_set:
# args += ['SET', ff.S]
#args += ['O', ff.Q]
#return AnonymousCircuit(args)
return ff
FF = DFF