def test_umull_z(self): mul = 3 * 0 pre_c = self.rf.read('APSR_C') pre_v = self.rf.read('APSR_V') self.assertEqual(self.rf.read('R1'), mul & Mask(32)) self.assertEqual(self.rf.read('R2'), (mul >> 32) & Mask(32)) self._checkFlagsNZCV(0, 1, pre_c, pre_v)
def test_umull_max(self): mul = 0xfffffffe**2 pre_c = self.rf.read('APSR_C') pre_v = self.rf.read('APSR_V') self.assertEqual(self.rf.read('R1'), mul & Mask(32)) self.assertEqual(self.rf.read('R2'), mul >> 32) self._checkFlagsNZCV(1, 0, pre_c, pre_v)
def test_umull_still32(self): mul = 2 * 2 pre_c = self.rf.read('APSR_C') pre_v = self.rf.read('APSR_V') self.assertEqual(self.rf.read('R1'), mul & Mask(32)) self.assertEqual(self.rf.read('R2'), mul >> 32) self._checkFlagsNZCV(0, 0, pre_c, pre_v)
def test_ldrsb_reg_off_neg(self): self.cpu.stack_push(0x2ff) self.cpu.stack_push(48) self.cpu.execute() self.assertEqual(self.rf.read('R1'), Mask(32))
def test_ldrsb_reg_off_neg(self): self.cpu.stack_push(0x2ff) self.cpu.stack_push(48) emulate_next(self.cpu) self.assertEqual(self.rf.read('R1'), Mask(32))