from loam.boards.icestick import IceStick
icestick = IceStick()
icestick.Clock.on()
for i in range(8):
icestick.J3[i].output().on()
main = icestick.main()
valid = 1
counter = mantle.CounterModM(103, 8)
baud = counter.COUT
count = mantle.Counter(4, has_ce=True, has_reset=True)
done = mantle.Decode(15, 4)(count.O)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, valid, run.O)
run(run_n, ce=baud)
reset = mantle.LUT2(mantle.I0 & ~mantle.I1)(done, run)
count(ce=baud, reset=reset)
m.wire(main.CLKIN, main.J3[0])
m.wire(baud, main.J3[1])
m.wire(run, main.J3[2])
m.wire(done, main.J3[3])
m.wire(count.O, main.J3[4:8])
def definition(io):
# IF - get cycle_id, label_index_id
controller = Controller()
reg_1_cycle = mantle.Register(n)
reg_1_control = mantle.DFF(init=1)
wire(io.CLK, controller.CLK)
wire(io.CLK, reg_1_cycle.CLK)
wire(io.CLK, reg_1_control.CLK)
reg_1_idx = controller.IDX
wire(controller.CYCLE, reg_1_cycle.I)
wire(1, reg_1_control.I)
# RR - get weight block, image block of N bits
readROM = ReadRom()
wire(reg_1_idx, readROM.IDX)
wire(reg_1_cycle.O, readROM.CYCLE)
reg_2 = mantle.Register(N + b + n)
reg_2_control = mantle.DFF()
reg_2_weight = readROM.WEIGHT
wire(io.CLK, reg_2.CLK)
wire(io.CLK, readROM.CLK)
wire(io.CLK, reg_2_control.CLK)
wire(readROM.IMAGE, reg_2.I[:N])
wire(reg_1_idx, reg_2.I[N:N + b])
wire(reg_1_cycle.O, reg_2.I[N + b:])
wire(reg_1_control.O, reg_2_control.I)
# EX - NXOr for multiplication, pop count and accumulate the result for activation
multiplier = mantle.NXOr(height=2, width=N)
bit_counter = DefineBitCounter(N)()
adder = mantle.Add(n_bc_adder, cin=False, cout=False)
mux_for_adder_0 = mantle.Mux(height=2, width=n_bc_adder)
mux_for_adder_1 = mantle.Mux(height=2, width=n_bc_adder)
reg_3_1 = mantle.Register(n_bc_adder)
reg_3_2 = mantle.Register(b + n)
wire(io.CLK, reg_3_1.CLK)
wire(io.CLK, reg_3_2.CLK)
wire(reg_2_weight, multiplier.I0)
wire(reg_2.O[:N], multiplier.I1)
wire(multiplier.O, bit_counter.I)
wire(bits(0, n_bc_adder), mux_for_adder_0.I0)
wire(bit_counter.O, mux_for_adder_0.I1[:n_bc])
if n_bc_adder > n_bc:
wire(bits(0, n_bc_adder - n_bc), mux_for_adder_0.I1[n_bc:])
# only when data read is ready (i.e. control signal is high), accumulate the pop count result
wire(reg_2_control.O, mux_for_adder_0.S)
wire(reg_3_1.O, mux_for_adder_1.I0)
wire(bits(0, n_bc_adder), mux_for_adder_1.I1)
if n == 4:
comparison_3 = SB_LUT4(LUT_INIT=int('0'*15+'1', 2))
wire(reg_2.O[N+b:], bits([comparison_3.I0, comparison_3.I1, comparison_3.I2, comparison_3.I3]))
else:
comparison_3 = mantle.EQ(n)
wire(reg_2.O[N+b:], comparison_3.I0)
wire(bits(0, n), comparison_3.I1)
wire(comparison_3.O, mux_for_adder_1.S)
wire(mux_for_adder_0.O, adder.I0)
wire(mux_for_adder_1.O, adder.I1)
wire(adder.O, reg_3_1.I)
wire(reg_2.O[N:], reg_3_2.I)
# CF - classify the image
classifier = Classifier()
reg_4 = mantle.Register(n + b)
reg_4_idx = classifier.O
wire(io.CLK, classifier.CLK)
wire(io.CLK, reg_4.CLK)
wire(reg_3_1.O, classifier.I)
wire(reg_3_2.O[:b], classifier.IDX)
wire(reg_3_2.O, reg_4.I)
# WB - wait to show the result until the end
reg_5 = mantle.Register(b, has_ce=True)
comparison_5_1 = mantle.EQ(b)
comparison_5_2 = mantle.EQ(n)
and_gate = mantle.And()
wire(io.CLK, reg_5.CLK)
wire(reg_4_idx, reg_5.I)
wire(reg_4.O[:b], comparison_5_1.I0)
wire(bits(num_classes - 1, b), comparison_5_1.I1)
wire(reg_4.O[b:], comparison_5_2.I0)
wire(bits(num_cycles - 1, n), comparison_5_2.I1)
wire(comparison_5_1.O, and_gate.I0)
wire(comparison_5_2.O, and_gate.I1)
wire(and_gate.O, reg_5.CE)
wire(reg_5.O, io.O)
# latch the light indicating the end
reg_6 = mantle.DFF()
wire(io.CLK, reg_6.CLK)
or_gate = mantle.Or()
wire(and_gate.O, or_gate.I0)
wire(reg_6.O, or_gate.I1)
wire(or_gate.O, reg_6.I)
wire(reg_6.O, io.D)
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(ready, start, cap_done,
burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 4, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(tf_size + 2, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
uart = UART(8)
uart_load = mantle.LUT2(I0 & ~I1)(load, tx_done)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=uart_load)
# wire output
m.wire(uart, cam.UART)