def definition(io):
edge_r = rising(io.SCK)
edge_f = falling(io.SCK)
# pixels come 16 bits (high and low byte) at a time
bit_counter = mantle.Counter(4, has_ce=True, has_reset=True)
m.wire(edge_r, bit_counter.CE)
# find when the high and low byte are valid
low = mantle.Decode(15, 4)(bit_counter.O)
high = mantle.Decode(7, 4)(bit_counter.O)
# shift registers to store high and low byte
low_byte = mantle.PIPO(8, has_ce=True)
high_byte = mantle.PIPO(8, has_ce=True)
low_byte(0, io.DATA, low)
high_byte(0, io.DATA, high)
m.wire(low, low_byte.CE)
m.wire(high, high_byte.CE)
# assemble the 16-bit RGB565 value
px_bits = (m.uint(mantle.LSL(16)((m.uint(m.concat(high_byte.O, zeros))), m.bits(8, 4)))
+ m.uint(m.concat(low_byte.O, zeros)))
# extract the values for each color
r_val = m.uint(mantle.LSR(16)((px_bits & RMASK), m.bits(11, 4)))
g_val = m.uint(mantle.LSR(16)((px_bits & GMASK), m.bits(5, 4)))
b_val = m.uint(px_bits & BMASK)
# sum them to get grayscale (0 to 125)
px_val = (r_val + g_val + b_val)
# --------------------------UART OUTPUT---------------------------- #
# run 16-bit UART at 2x speed
baud = edge_r | edge_f
# reset at start of pixel transfer
ff1 = mantle.FF(has_ce=True)
m.wire(baud, ff1.CE)
u_reset = mantle.LUT2(I0 & ~I1)(io.VALID, ff1(io.VALID))
m.wire(u_reset, bit_counter.RESET)
# generate load signal
ff2 = mantle.FF(has_ce=True)
m.wire(baud, ff2.CE)
load = mantle.LUT3(I0 & I1 & ~I2)(io.VALID, high, ff2(high))
uart = UART(16)
uart(CLK=io.CLK, BAUD=baud, DATA=px_val, LOAD=load)
m.wire(px_val, io.PXV)
m.wire(uart, io.UART)
m.wire(load, io.LOAD)
class Main(m.Circuit):
if target == 'coreir':
test = mantle.LUT([0, 0, 0, 1], 2)
else:
test = mantle.LUT2([0, 0, 0, 1])
if target == 'spartan3' or target == 'spartan6':
assert 'LUT2(INIT=0x8)' == repr(test)
elif target == 'ice40':
assert 'AnonymousCircuitType("I0", .I0, "I1", .I1, "O", .O)' == strip_anonymous_circuits(
repr(test))
elif target == 'coreir':
assert 'LUT2_8()' == repr(test)
def test_lut2():
target = magma.mantle_target
if target == 'coreir':
test = mantle.LUT([0, 0, 0, 1], 2)
else:
test = mantle.LUT2([0, 0, 0, 1])
if target == 'spartan3' or target == 'spartan6':
assert ' = LUT2(INIT=0x8)' == repr(test)
elif target == 'ice40':
assert 'AnonymousCircuitType("I0", .I0, "I1", .I1, "O", .O)' == repr(
test)
elif target == 'coreir':
assert ' = LUT2_8()' == repr(test)
def definition(cam):
edge_f = falling(cam.SCK)
edge_r = rising(cam.SCK)
# ROM to store commands
rom_index = mantle.Counter(4, has_ce=True)
rom = ROM16(4, init, rom_index.O)
# Message length is 16 bits, setup counter to generate done signal
# after EOM
done_counter = mantle.Counter(5, has_ce=True, has_reset=True)
count = done_counter.O
done = mantle.Decode(16, 5)(count)
# State machine to generate run signal (enable)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, trigger, run)
run(run_n)
m.wire(edge_f, run.CE)
# Reset the message length counter after done
run_reset = mantle.LUT2(I0 | ~I1)(done, run)
done_counter(CE=edge_r, RESET=run_reset)
# State variables for high-level state machine
ready = mantle.LUT2(~I0 & I1)(run, edge_f)
start = mantle.ULE(4)(rom_index.O, m.uint(3, 4))
burst = mantle.UGE(4)(rom_index.O, m.uint(9, 4))
# Shift register to store 16-bit command|data to send
mosi = mantle.PISO(16, has_ce=True)
# SPI enable is negative of load-don't load and shift out data at the
# same time
enable = mantle.LUT3(I0 & ~I1 & ~I2)(trigger, run, burst)
mosi(~burst, rom.O, enable)
m.wire(edge_f, mosi.CE)
# Shit register to read in 8-bit data
miso = mantle.SIPO(8, has_ce=True)
miso(cam.MISO)
valid = mantle.LUT2(~I0 & I1)(enable, edge_r)
m.wire(valid, miso.CE)
# Capture done state variable
cap_done = mantle.SRFF(has_ce=True)
cap_done(mantle.EQ(8)(miso.O, m.bits(0x08, 8)), 0)
m.wire(enable & edge_r, cap_done.CE)
# Use state variables to determine what commands are sent (how)
increment = mantle.LUT4(I0 & (I1 | I2) & ~I3)(
ready, start, cap_done, burst)
m.wire(increment, rom_index.CE)
# wire outputs
m.wire(enable, cam.EN)
m.wire(mosi.O, cam.MOSI)
m.wire(miso.O, cam.DATA)
m.wire(burst, cam.VALID)
# --------------------------UART OUTPUT---------------------------- #
# run UART at 2x SPI rate to allow it to keep up
baud = edge_r | edge_f
# reset when SPI burst read (image transfer) begins
ff = mantle.FF(has_ce=True)
m.wire(edge_r, ff.CE)
u_reset = mantle.LUT2(I0 & ~I1)(burst, ff(burst))
# UART data out every 8 bits
u_counter = mantle.CounterModM(8, 3, has_ce=True, has_reset=True)
u_counter(CE=edge_r, RESET=u_reset)
load = burst & rising(u_counter.COUT)
uart = UART(8)
uart(CLK=cam.CLK, BAUD=baud, DATA=miso, LOAD=load)
# wire output
m.wire(uart, cam.UART)
# generate signal for when transfer is done
data_count = mantle.Counter(18, has_ce=True)
tx_done = mantle.SRFF(has_ce=True)
# transfer has size 153600 bytes, first 2 bytes are ignored
tx_done(mantle.EQ(18)(data_count.O, m.bits(153602, 18)), 0)
m.wire(load, tx_done.CE)
m.wire(load, data_count.CE)
# wire output
m.wire(tx_done, cam.DONE)
rom = ROM(4, init, printf.O)
data = m.array([rom.O[7], rom.O[6], rom.O[5], rom.O[4],
rom.O[3], rom.O[2], rom.O[1], rom.O[0], 0])
counter = mantle.CounterModM(103, 8)
baud = counter.COUT
count = mantle.Counter(4, has_ce=True, has_reset=True)
decode = mantle.Decode(15, 4)
done = decode(count.O)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0,0,1,0, 1,0,1,0])
run_n(done, valid, run.O)
run(run_n, ce=baud)
reset = mantle.LUT2(mantle.I0&~mantle.I1)(done, run)
count(CE=baud, RESET=reset)
shift = mantle.PISO(9, has_ce=True)
load = mantle.LUT2(mantle.I0&~mantle.I1)(valid,run)
shift(1,data,load)
m.wire(baud, shift.CE)
ready = mantle.LUT2(~mantle.I0 & mantle.I1)(run, baud)
m.wire(ready, printf.CE)
m.wire(shift, main.TX)
from loam.boards.icestick import IceStick
icestick = IceStick()
icestick.Clock.on()
for i in range(8):
icestick.J3[i].output().on()
main = icestick.main()
valid = 1
counter = mantle.CounterModM(103, 8)
baud = counter.COUT
count = mantle.Counter(4, has_ce=True, has_reset=True)
done = mantle.Decode(15, 4)(count.O)
run = mantle.DFF(has_ce=True)
run_n = mantle.LUT3([0, 0, 1, 0, 1, 0, 1, 0])
run_n(done, valid, run.O)
run(run_n, ce=baud)
reset = mantle.LUT2(mantle.I0 & ~mantle.I1)(done, run)
count(ce=baud, reset=reset)
m.wire(main.CLKIN, main.J3[0])
m.wire(baud, main.J3[1])
m.wire(run, main.J3[2])
m.wire(done, main.J3[3])
m.wire(count.O, main.J3[4:8])