def test(request, silent=True):
veriloggen.reset()
simtype = request.config.getoption('--sim')
rslt = matrix_conv2d_padding.run(
act_shape,
weight_shape,
bias_shape,
scale_shape,
act_dtype,
weight_dtype,
bias_dtype,
scale_dtype,
out_dtype,
stride,
rshift_mul,
rshift_sum,
rshift_out,
act_func,
padding,
par_ich,
par_och,
par_col,
par_row,
concur_och,
stationary,
input_ram_size,
filter_ram_size,
bias_ram_size,
scale_ram_size,
out_ram_size,
axi_datawidth,
silent,
filename=None,
simtype=simtype,
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
verify_rslt = rslt.splitlines()[-1]
assert (verify_rslt == '# verify: PASSED')
rslt = matrix_conv2d_padding.run(
act_shape,
weight_shape,
bias_shape,
scale_shape,
act_dtype,
weight_dtype,
bias_dtype,
scale_dtype,
out_dtype,
stride,
rshift_mul,
rshift_sum,
rshift_out,
act_func,
padding,
par_ich,
par_och,
par_col,
par_row,
concur_och,
stationary,
input_ram_size,
filter_ram_size,
bias_ram_size,
scale_ram_size,
out_ram_size,
axi_datawidth,
silent=False,
filename='tmp.v',
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
