def test_and():
alu = ALU()
ret, flag = alu(0x33, 0x55, Flag(get_flag()), 'and')
assert ret == 0x11 and flag.data == get_flag()
ret, flag = alu(0x33, 0xcc, Flag(get_flag()), 'and')
assert ret == 0x00 and flag.data == get_flag(z=1)
ret, flag = alu(0xff, 0x88, Flag(get_flag()), 'and')
assert ret == 0x88 and flag.data == get_flag(n=1)
def test_inc():
alu = ALU()
ret, flag = alu(0x64, None, Flag(get_flag()), 'inc')
assert ret == 0x65 and flag.data == get_flag()
ret, flag = alu(0xff, None, Flag(get_flag()), 'inc')
assert ret == 0x00 and flag.data == get_flag(z=1)
ret, flag = alu(0x7f, None, Flag(get_flag()), 'inc')
assert ret == 0x80 and flag.data == get_flag(n=1)
def test_cmp():
alu = ALU()
ret, flag = alu(0x55, 0x33, Flag(get_flag()), 'cmp')
assert ret == 0x55 and flag.data == get_flag(n=0, z=0, c=0)
ret, flag = alu(0x33, 0x55, Flag(get_flag()), 'cmp')
assert ret == 0x33 and flag.data == get_flag(n=1, z=0, c=1)
ret, flag = alu(0x33, 0x33, Flag(get_flag()), 'cmp')
assert ret == 0x33 and flag.data == get_flag(n=0, z=1, c=0)
def test_eor():
alu = ALU()
ret, flag = alu(0x33, 0x55, Flag(get_flag()), 'eor')
assert ret == 0x66 and flag.data == get_flag()
ret, flag = alu(0x33, 0xcc, Flag(get_flag()), 'eor')
assert ret == 0xff and flag.data == get_flag(n=1)
ret, flag = alu(0xff, 0xff, Flag(get_flag()), 'eor')
assert ret == 0x00 and flag.data == get_flag(z=1)
def test_ora():
alu = ALU()
ret, flag = alu(0x33, 0x55, Flag(get_flag()), 'ora')
assert ret == 0x77 and flag.data == get_flag()
ret, flag = alu(0x33, 0xcc, Flag(get_flag()), 'ora')
assert ret == 0xff and flag.data == get_flag(n=1)
ret, flag = alu(0x00, 0x00, Flag(get_flag()), 'ora')
assert ret == 0x00 and flag.data == get_flag(z=1)
def test_ror():
alu = ALU()
ret, flag = alu(0x22, None, Flag(get_flag()), 'ror')
assert ret == 0x11 and flag.data == get_flag()
ret, flag = alu(0x00, None, Flag(get_flag()), 'ror')
assert ret == 0x00 and flag.data == get_flag(z=1)
ret, flag = alu(0x11, None, Flag(get_flag()), 'ror')
assert ret == 0x08 and flag.data == get_flag(c=1)
ret, flag = alu(0x01, None, Flag(get_flag(c=1)), 'ror')
assert ret == 0x80 and flag.data == get_flag(n=1, c=1)
def test_asl():
alu = ALU()
ret, flag = alu(0x33, None, Flag(get_flag()), 'asl')
assert ret == 0x66 and flag.data == get_flag()
ret, flag = alu(0x70, None, Flag(get_flag()), 'asl')
assert ret == 0xe0 and flag.data == get_flag(n=1)
ret, flag = alu(0x00, None, Flag(get_flag()), 'asl')
assert ret == 0x00 and flag.data == get_flag(z=1)
ret, flag = alu(0x80, None, Flag(get_flag()), 'asl')
assert ret == 0x00 and flag.data == get_flag(z=1, c=1)
def test_dec():
alu = ALU()
ret, flag = alu(0x64, None, Flag(get_flag()), 'dec')
assert ret == 0x63 and flag.data == get_flag()
ret, flag = alu(0xa4, None, Flag(get_flag()), 'dec')
assert ret == 0xa3 and flag.data == get_flag(n=1)
ret, flag = alu(0x01, None, Flag(get_flag()), 'dec')
assert ret == 0x00 and flag.data == get_flag(z=1)
ret, flag = alu(0x00, None, Flag(get_flag()), 'dec')
assert ret == 0xff and flag.data == get_flag(n=1)
ret, flag = alu(0x80, None, Flag(get_flag()), 'dec')
assert ret == 0x7f and flag.data == get_flag(n=0)
def test_bit():
alu = ALU()
ret, flag = alu(0x55, 0x33, Flag(get_flag()), 'bit')
assert ret == 0x55 and flag.data == get_flag(n=0, v=0, z=0)
ret, flag = alu(0x55, 0x22, Flag(get_flag()), 'bit')
assert ret == 0x55 and flag.data == get_flag(n=0, v=0, z=1)
ret, flag = alu(0x80, 0x80, Flag(get_flag()), 'bit')
assert ret == 0x80 and flag.data == get_flag(n=1, v=0, z=0)
ret, flag = alu(0x40, 0x40, Flag(get_flag()), 'bit')
assert ret == 0x40 and flag.data == get_flag(n=0, v=1, z=0)
ret, flag = alu(0xc0, 0xc0, Flag(get_flag()), 'bit')
assert ret == 0xc0 and flag.data == get_flag(n=1, v=1, z=0)
def test_adc():
alu = ALU()
ret, flag = alu(0x0d, 0xd3, Flag(get_flag(c=1)), 'adc')
assert ret == 0xe1 and flag.data == get_flag(n=1, v=0, z=0, c=0)
ret, flag = alu(0xfe, 0x06, Flag(get_flag(c=1)), 'adc')
assert ret == 0x05 and flag.data == get_flag(n=0, v=0, z=0, c=1)
ret, flag = alu(0x80, 0x80, Flag(get_flag(c=0)), 'adc')
assert ret == 0x00 and flag.data == get_flag(n=0, v=1, z=1, c=1)
ret, flag = alu(0x05, 0x07, Flag(get_flag(c=0)), 'adc')
assert ret == 0x0c and flag.data == get_flag(n=0, v=0, z=0, c=0)
ret, flag = alu(0x7f, 0x02, Flag(get_flag(c=0)), 'adc')
assert ret == 0x81 and flag.data == get_flag(n=1, v=1, z=0, c=0)
ret, flag = alu(0x05, 0xfd, Flag(get_flag(c=0)), 'adc')
assert ret == 0x02 and flag.data == get_flag(n=0, v=0, z=0, c=1)
ret, flag = alu(0x05, 0xf9, Flag(get_flag(c=0)), 'adc')
assert ret == 0xfe and flag.data == get_flag(n=1, v=0, z=0, c=0)
ret, flag = alu(0xfb, 0xf9, Flag(get_flag(c=0)), 'adc')
assert ret == 0xf4 and flag.data == get_flag(n=1, v=0, z=0, c=1)
ret, flag = alu(0xbe, 0xbf, Flag(get_flag(c=0)), 'adc')
assert ret == 0x7d and flag.data == get_flag(n=0, v=1, z=0, c=1)
def test_tha():
alu = ALU()
ret, flag = alu(0xff, None, Flag(get_flag(n=1)), 'tha')
assert ret == 0xff and flag.data == get_flag(n=1)
def test_sbc():
alu = ALU()
ret, flag = alu(0x05, 0x03, Flag(get_flag()), 'sbc')
assert ret == 0x02 and flag.data == get_flag(n=0, v=0, z=0, c=1)
ret, flag = alu(0x05, 0x06, Flag(get_flag()), 'sbc')
assert ret == 0xff and flag.data == get_flag(n=1, v=0, z=0, c=0)
def flag(self):
return Flag(self.p.data)
def __call__(self, data, controller, dbe=True):
# Data Bus
db_src = {
'm': data,
'a': self.a.data,
'x': self.x.data,
'y': self.y.data,
't': self.t.data,
'p': self.p.data,
'pcl': self.pcl.data,
'pch': self.pch.data,
}.get(controller.db_src, None)
if dbe:
self.db(db_src)
self.dl(self.db.data, controller.dl_we)
# Instruction Register
self.ir(data, controller.ir_we)
# Program Counter Increment/Add
pcl_add, pch_add = self.pcadder(self.pcl.data, self.pch.data, data,
controller.pcadder_ctrl)
# Program Counter
pcl_src = {
'm': self.dl.data,
't': self.t.data,
'padr': pcl_add,
}.get(controller.pcl_src, None)
self.pcl(pcl_src, controller.pcl_we)
pch_src = {
'm': self.dl.data,
'padr': pch_add,
}.get(controller.pch_src, None)
self.pch(pch_src, controller.pch_we)
# ALU
alu_src_a = {
'a': self.a.data,
'x': self.x.data,
'y': self.y.data,
's': self.s.data,
't': self.t.data,
}.get(controller.alu_src_a, 0x00)
alu_src_b = {
'm': self.dl.data,
't': self.t.data,
}.get(controller.alu_src_b, 0x00)
alu_out, flag_alu = self.alu(alu_src_a, alu_src_b, Flag(self.p.data),
controller.alu_ctrl)
self._alu_out = alu_out # for debug
# Registers
reg_src = {
'm': self.dl.data,
'alu': alu_out,
}.get(controller.reg_src, None)
self.a(reg_src, controller.a_we) # Accumulator
self.x(reg_src, controller.x_we) # Index X Register
self.y(reg_src, controller.y_we) # Index Y Register
self.s(reg_src, controller.s_we) # Stack Point Register
self.t(reg_src, controller.t_we) # Temporary Register
# Processor Status Register
p_src = {
'm': self.dl.data,
'set': self.p.data | controller.p_mask,
'clr': self.p.data & ~controller.p_mask,
'alu': flag_alu.data,
}.get(controller.p_src, self.p.data)
self.p(p_src, True)
# Address Bus
str_ab = self.ab
abl_src = {
'm': self.dl.data,
's': self.s.data,
't': self.t.data,
'pcl': self.pcl.data,
'alu': alu_out,
'fe': 0xfe,
'ff': 0xff,
}.get(controller.abl_src, None)
self.abl(abl_src, controller.abl_we)
abh_src = {
'm': self.dl.data,
'pch': self.pch.data,
'alu': alu_out,
'0': 0x00,
'1': 0x01,
'ff': 0xff,
}.get(controller.abh_src, None)
self.abh(abh_src, controller.abh_we)
return self.db.data, str_ab if controller.r_w == 'w' else self.ab