def memory_controller(use_mmu):
instance = mhstools.MHSPCore("reconos_memif_memory_controller")
instance.addEntry("PARAMETER", "INSTANCE",
"reconos_memif_memory_controller_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
if use_mmu:
instance.addEntry("PARAMETER", "C_USE_MMU_PORT", "TRUE")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Mmu",
"reconos_memif_mmu_0_CTRL_FIFO_Mmu")
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Mmu",
"reconos_memif_memory_controller_0_MEMIF_FIFO_Mmu")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Hwt",
"reconos_memif_mmu_0_CTRL_FIFO_Out")
else:
instance.addEntry("PARAMETER", "C_USE_MMU_PORT", "FALSE")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Hwt",
"reconos_memif_burst_converter_0_CTRL_FIFO_Out")
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Mem2Hwt",
"reconos_memif_arbiter_0_MEMIF_FIFO_Out_Mem2Hwt")
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Hwt2Mem",
"reconos_memif_arbiter_0_MEMIF_FIFO_Out_Hwt2Mem")
instance.addEntry("BUS_INTERFACE", "M_AXI", MEMORY_BUS)
instance.addEntry("PORT", "M_AXI_ACLK", DEFAULT_CLK)
instance.addEntry("PORT", "MEMCTRL_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "MEMCTRL_Rst",
"reconos_proc_control_0_PROC_Sys_Rst")
return instance
def proc_control(num_hwts, use_mmu):
instance = mhstools.MHSPCore("reconos_proc_control")
instance.addEntry("PARAMETER", "INSTANCE", "reconos_proc_control_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_BASEADDR",
"0x%x" % PROC_CONTROL_BASE_ADDR)
instance.addEntry(
"PARAMETER", "C_HIGHADDR",
"0x%x" % (PROC_CONTROL_BASE_ADDR + PROC_CONTROL_MEM_SIZE - 1))
instance.addEntry("PARAMETER", "C_NUM_HWTS", num_hwts)
instance.addEntry("BUS_INTERFACE", "S_AXI", HWT_BUS)
instance.addEntry("PORT", "S_AXI_ACLK", DEFAULT_CLK)
instance.addEntry("PORT", "PROC_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "PROC_Rst", DEFAULT_RST)
for i in range(num_hwts):
instance.addEntry("PORT", "PROC_Hwt_Rst_%d" % i,
"reconos_proc_control_0_PROC_Hwt_Rst_%d" % i)
instance.addEntry("PORT", "PROC_Sys_Rst",
"reconos_proc_control_0_PROC_Sys_Rst")
if use_mmu:
instance.addEntry("PORT", "PROC_Pgf_Int",
"reconos_proc_control_0_PROC_Pgf_Int")
instance.addEntry("PORT", "MMU_Pgf", "reconos_memif_mmu_0_MMU_Pgf")
instance.addEntry("PORT", "MMU_Fault_Addr",
"reconos_memif_mmu_0_MMU_Fault_Addr")
instance.addEntry("PORT", "MMU_Retry",
"reconos_proc_control_0_MMU_Retry")
instance.addEntry("PORT", "MMU_Pgd", "reconos_proc_control_0_MMU_Pgd")
instance.addEntry("PORT", "MMU_Tlb_Hits",
"reconos_memif_mmu_0_MMU_Tlb_Hits")
instance.addEntry("PORT", "MMU_Tlb_Misses",
"reconos_memif_mmu_0_MMU_Tlb_Misses")
return instance
def mmu(arch):
instance = mhstools.MHSPCore("reconos_memif_mmu_" + arch)
instance.addEntry("PARAMETER", "INSTANCE", "reconos_memif_mmu_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_TLB_SIZE", 16)
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_In",
"reconos_memif_burst_converter_0_CTRL_FIFO_Out")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Out",
"reconos_memif_mmu_0_CTRL_FIFO_Out")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Mmu",
"reconos_memif_mmu_0_CTRL_FIFO_Mmu")
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Mmu",
"reconos_memif_memory_controller_0_MEMIF_FIFO_Mmu")
instance.addEntry("PORT", "MMU_Pgf", "reconos_memif_mmu_0_MMU_Pgf")
instance.addEntry("PORT", "MMU_Fault_Addr",
"reconos_memif_mmu_0_MMU_Fault_Addr")
instance.addEntry("PORT", "MMU_Retry", "reconos_proc_control_0_MMU_Retry")
instance.addEntry("PORT", "MMU_Pgd", "reconos_proc_control_0_MMU_Pgd")
instance.addEntry("PORT", "MMU_Tlb_Hits",
"reconos_memif_mmu_0_MMU_Tlb_Hits")
instance.addEntry("PORT", "MMU_Tlb_Misses",
"reconos_memif_mmu_0_MMU_Tlb_Misses")
instance.addEntry("PORT", "MMU_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "MMU_Rst", "reconos_proc_control_0_PROC_Sys_Rst")
return instance
def memif_fifo(num, direction):
instance = mhstools.MHSPCore("reconos_fifo")
instance.addEntry("PARAMETER", "INSTANCE",
"reconos_memif_fifo_%d_" % num + direction)
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_FIFO_DEPTH", DEFAULT_MEMIF_FIFO_DEPTH)
instance.addEntry("BUS_INTERFACE", "FIFO_M",
"reconos_memif_fifo_%d_" % num + direction + "_FIFO_M")
instance.addEntry("BUS_INTERFACE", "FIFO_S",
"reconos_memif_fifo_%d_" % num + direction + "_FIFO_S")
instance.addEntry("PORT", "FIFO_Rst",
"reconos_proc_control_0_PROC_Hwt_Rst_%d" % num)
instance.addEntry("PORT", "FIFO_S_Clk", DEFAULT_CLK)
return instance
def burst_converter():
instance = mhstools.MHSPCore("reconos_memif_burst_converter")
instance.addEntry("PARAMETER", "INSTANCE",
"reconos_memif_burst_converter_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_PAGE_SIZE", 4096)
instance.addEntry("PARAMETER", "C_MAX_BURST_SIZE", 256)
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_In",
"reconos_memif_arbiter_0_CTRL_FIFO_Out")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Out",
"reconos_memif_burst_converter_0_CTRL_FIFO_Out")
instance.addEntry("PORT", "BCONV_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "BCONV_Rst",
"reconos_proc_control_0_PROC_Sys_Rst")
return instance
def hwt_static(name, num, version, use_mem):
instance = mhstools.MHSPCore(name)
instance.addEntry("PARAMETER", "INSTANCE", "hwt_static_%d" % num)
instance.addEntry("PARAMETER", "HW_VER", version)
instance.addEntry("BUS_INTERFACE", "OSIF_FIFO_Sw2Hw",
"reconos_osif_fifo_%d_sw2hw_FIFO_S" % num)
instance.addEntry("BUS_INTERFACE", "OSIF_FIFO_Hw2Sw",
"reconos_osif_fifo_%d_hw2sw_FIFO_M" % num)
if use_mem:
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Hwt2Mem",
"reconos_memif_fifo_%d_hwt2mem_FIFO_M" % num)
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Mem2Hwt",
"reconos_memif_fifo_%d_mem2hwt_FIFO_S" % num)
instance.addEntry("PORT", "HWT_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "HWT_Rst",
"reconos_proc_control_0_PROC_Hwt_Rst_%d" % num)
return instance
def osif(num_hwts):
instance = mhstools.MHSPCore("reconos_osif")
instance.addEntry("PARAMETER", "INSTANCE", "reconos_osif_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_BASEADDR", "0x%x" % OSIF_FIFO_BASE_ADDR)
instance.addEntry("PARAMETER", "C_HIGHADDR",
"0x%x" % (OSIF_FIFO_BASE_ADDR + OSIF_FIFO_MEM_SIZE - 1))
instance.addEntry("PARAMETER", "C_NUM_FIFOS", num_hwts)
instance.addEntry("PARAMETER", "C_FIFO_WIDTH", "32")
for i in range(num_hwts):
instance.addEntry("BUS_INTERFACE", "FIFO_S_%d" % i,
"reconos_osif_fifo_%d_hw2sw_FIFO_S" % i)
instance.addEntry("BUS_INTERFACE", "FIFO_M_%d" % i,
"reconos_osif_fifo_%d_sw2hw_FIFO_M" % i)
instance.addEntry("BUS_INTERFACE", "S_AXI", HWT_BUS)
instance.addEntry("PORT", "S_AXI_ACLK", DEFAULT_CLK)
return instance
def osif_intc(num_hwts):
instance = mhstools.MHSPCore("reconos_osif_intc")
instance.addEntry("PARAMETER", "INSTANCE", "reconos_osif_intc_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_BASEADDR", "0x%x" % OSIF_INTC_BASE_ADDR)
instance.addEntry("PARAMETER", "C_HIGHADDR",
"0x%x" % (OSIF_INTC_BASE_ADDR + OSIF_INTC_MEM_SIZE - 1))
instance.addEntry("PARAMETER", "C_NUM_INTERRUPTS", num_hwts)
instance.addEntry("BUS_INTERFACE", "S_AXI", HWT_BUS)
instance.addEntry("PORT", "S_AXI_ACLK", DEFAULT_CLK)
instance.addEntry("PORT", "OSIF_INTC_Out",
"reconos_osif_intc_0_OSIF_INTC_Out")
for i in range(num_hwts):
instance.addEntry("PORT", "OSIF_INTC_In_%d" % i,
"reconos_osif_fifo_%d_hw2sw_FIFO_Has_Data" % i)
instance.addEntry("PORT", "OSIF_INTC_Rst",
"reconos_proc_control_0_PROC_Sys_Rst")
return instance
def arbiter(num_hwts):
instance = mhstools.MHSPCore("reconos_memif_arbiter")
instance.addEntry("PARAMETER", "INSTANCE", "reconos_memif_arbiter_0")
instance.addEntry("PARAMETER", "HW_VER", "1.00.a")
instance.addEntry("PARAMETER", "C_NUM_HWTS", num_hwts)
for i in range(num_hwts):
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_In_Hwt2Mem_%d" % i,
"reconos_memif_fifo_%d_hwt2mem_FIFO_S" % i)
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_In_Mem2Hwt_%d" % i,
"reconos_memif_fifo_%d_mem2hwt_FIFO_M" % i)
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Out_Mem2Hwt",
"reconos_memif_arbiter_0_MEMIF_FIFO_Out_Mem2Hwt")
instance.addEntry("BUS_INTERFACE", "MEMIF_FIFO_Out_Hwt2Mem",
"reconos_memif_arbiter_0_MEMIF_FIFO_Out_Hwt2Mem")
instance.addEntry("BUS_INTERFACE", "CTRL_FIFO_Out",
"reconos_memif_arbiter_0_CTRL_FIFO_Out")
instance.addEntry("PORT", "TCTRL_Clk", DEFAULT_CLK)
instance.addEntry("PORT", "TCTRL_Rst",
"reconos_proc_control_0_PROC_Sys_Rst")
return instance
