def __init__(self, platform): GenSoC.__init__(self, platform, clk_freq=80 * 1000000, cpu_reset_address=0x60000) platform.add_extension(_tester_io) self.submodules.crg = _CRG(platform) # BIOS is in SPI flash self.submodules.spiflash = spiflash.SpiFlash( platform.request("spiflash2x"), cmd=0xefef, cmd_width=16, addr_width=24, dummy=4) self.flash_boot_address = 0x70000 self.register_rom(self.spiflash.bus) # Use block RAM instead of SDRAM for now sys_ram_size = 32 * 1024 self.submodules.sys_ram = wishbone.SRAM(sys_ram_size) self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus) self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size) self.submodules.leds = gpio.GPIOOut( Cat(platform.request("user_led", i) for i in range(2))) self.submodules.test_inputs = gpio.GPIOIn(platform.request("inputs")) self.submodules.test_ttl = ttlgpio.TTLGPIO(platform.request("ttl")) self.submodules.dds = ad9858.AD9858(platform.request("dds")) self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
def __init__(self, dw, nrxslots=2, ntxslots=2): self.sink = Sink(eth_phy_description(dw)) self.source = Source(eth_phy_description(dw)) self.bus = wishbone.Interface() # # # # storage in SRAM sram_depth = buffer_depth // (dw // 8) self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) self.comb += [ Record.connect(self.sink, self.sram.sink), Record.connect(self.sram.source, self.source) ] # Wishbone interface wb_rx_sram_ifs = [ wishbone.SRAM(self.sram.writer.mems[n], read_only=True) for n in range(nrxslots) ] # TODO: FullMemoryWE should move to Mibuild wb_tx_sram_ifs = [ FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False)) for n in range(ntxslots) ] wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs wb_slaves = [] decoderoffset = log2_int(sram_depth) decoderbits = log2_int(len(wb_sram_ifs)) for n, wb_sram_if in enumerate(wb_sram_ifs): def slave_filter(a, v=n): return a[decoderoffset:decoderoffset + decoderbits] == v wb_slaves.append((slave_filter, wb_sram_if.bus)) self.submodules += wb_sram_if wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True) self.submodules += wb_con
def __init__(self): self.submodules.host = Host(64, root_id, endpoint_id, phy_debug=False, chipset_debug=False, host_debug=False) self.submodules.endpoint = Endpoint(self.host.phy) self.submodules.wishbone_bridge = WishboneBridge( self.endpoint, lambda a: 1) self.submodules.sram = wishbone.SRAM(1024, bus=self.wishbone_bridge.wishbone)
def __init__(self, platform, clk_freq=166 * 1000000, mac_address=0x10e2d5000000, ip_address="192.168.0.42"): clk_freq = int((1 / (platform.default_clk_period)) * 1000000000) SoC.__init__(self, platform, clk_freq, cpu_type="none", with_csr=True, csr_data_width=32, with_uart=False, with_identifier=True, with_timer=False) self.add_cpu_or_bridge( UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)) self.add_wb_master(self.cpu_or_bridge.wishbone) self.submodules.crg = CRG(platform.request(platform.default_clk_name)) # wishbone SRAM (to test Wishbone over UART and Etherbone) self.submodules.sram = wishbone.SRAM(1024) self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus) # ethernet PHY and UDP/IP stack self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq) self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq) if isinstance(platform.toolchain, XilinxVivadoToolchain): self.specials += [ Keep(self.crg.cd_sys.clk), Keep(self.phy.crg.cd_eth_rx.clk), Keep(self.phy.crg.cd_eth_tx.clk) ] platform.add_platform_command(""" create_clock -name sys_clk -period 6.0 [get_nets sys_clk] create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk] create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk] set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk] set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk] set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk] """)
def __init__(self): self.submodules.phy_model = phy.PHY(8, debug=False) self.submodules.mac_model = mac.MAC(self.phy_model, debug=False, loopback=False) self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=False) self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=False, loopback=False) self.submodules.udp_model = udp.UDP(self.ip_model, ip_address, debug=False, loopback=False) self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False) self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000) self.submodules.sram = wishbone.SRAM(1024) self.submodules.interconnect = wishbone.InterconnectPointToPoint( self.etherbone.master.bus, self.sram.bus) # use sys_clk for each clock_domain self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain() self.comb += [ self.cd_eth_rx.clk.eq(ClockSignal()), self.cd_eth_rx.rst.eq(ResetSignal()), self.cd_eth_tx.clk.eq(ClockSignal()), self.cd_eth_tx.rst.eq(ResetSignal()), ]
def __init__(self, platform, clk_freq, cpu_type="lm32", cpu_reset_address=0x00000000, integrated_rom_size=0, integrated_sram_size=4096, integrated_main_ram_size=0, shadow_base=0x80000000, with_csr=True, csr_data_width=8, csr_address_width=14, with_uart=True, uart_baudrate=115200, with_identifier=True, with_timer=True): self.platform = platform self.clk_freq = clk_freq self.cpu_type = cpu_type if integrated_rom_size: cpu_reset_address = 0 self.cpu_reset_address = cpu_reset_address self.integrated_rom_size = integrated_rom_size self.integrated_sram_size = integrated_sram_size self.integrated_main_ram_size = integrated_main_ram_size self.with_uart = with_uart self.uart_baudrate = uart_baudrate self.with_identifier = with_identifier self.shadow_base = shadow_base self.with_csr = with_csr self.csr_data_width = csr_data_width self.csr_address_width = csr_address_width self._memory_regions = [] # list of (name, origin, length) self._csr_regions = [ ] # list of (name, origin, busword, csr_list/Memory) self._constants = [] # list of (name, value) self._wb_masters = [] self._wb_slaves = [] if cpu_type != "none": if cpu_type == "lm32": self.add_cpu_or_bridge( lm32.LM32(platform, self.cpu_reset_address)) elif cpu_type == "or1k": self.add_cpu_or_bridge( mor1kx.MOR1KX(platform, self.cpu_reset_address)) else: raise ValueError("Unsupported CPU type: {}".format(cpu_type)) self.add_wb_master(self.cpu_or_bridge.ibus) self.add_wb_master(self.cpu_or_bridge.dbus) if integrated_rom_size: self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True) self.register_rom(self.rom.bus, integrated_rom_size) if integrated_sram_size: self.submodules.sram = wishbone.SRAM(integrated_sram_size) self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if integrated_main_ram_size: self.submodules.main_ram = wishbone.SRAM( integrated_main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) if with_csr: self.submodules.wishbone2csr = wishbone2csr.WB2CSR( bus_csr=csr.Interface(csr_data_width, csr_address_width)) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) if with_uart: self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate) self.submodules.uart = uart.UART(self.uart_phy) if with_identifier: platform_id = 0x554E if not hasattr( platform, "identifier") else platform.identifier self.submodules.identifier = identifier.Identifier( platform_id, int(clk_freq)) if with_timer: self.submodules.timer0 = timer.Timer()