def request(self, name, number=None):
resource = _lookup(self.available, name, number)
rt, ri = _resource_type(resource)
if number is None:
resource_name = name
else:
resource_name = name + str(number)
if isinstance(rt, int):
obj = Signal(rt, name_override=resource_name)
else:
obj = Record(rt, name=resource_name)
for name, inverted in ri:
if inverted:
getattr(obj, name).inverted = True
for element in resource[2:]:
if isinstance(element, Inverted):
if isinstance(obj, Signal):
obj.inverted = True
if isinstance(element, PlatformInfo):
obj.platform_info = element.info
break
self.available.remove(resource)
self.matched.append((resource, obj))
return obj
def request(self, name, number=None):
resource = _lookup(self.available, name, number)
rt, ri = _resource_type(resource)
if number is None:
resource_name = name
else:
resource_name = name + str(number)
if isinstance(rt, int):
obj = Signal(rt, name_override=resource_name)
else:
obj = Record(rt, name=resource_name)
for name, inverted in ri:
if inverted:
getattr(obj, name).inverted = True
for element in resource[2:]:
if isinstance(element, Inverted):
if isinstance(obj, Signal):
obj.inverted = True
if isinstance(element, PlatformInfo):
obj.platform_info = element.info
break
self.available.remove(resource)
self.matched.append((resource, obj))
return obj
class Blinker(Module):
def __init__(self, led, maxperiod1, maxperiod2, select):
self.counter = Signal(max=maxperiod1 + 1)
self.period1 = Signal(max=maxperiod1 + 1)
self.period2 = Signal(max=maxperiod2 + 1)
self.selector = Signal(max=select + 1)
self.period = Signal(max=maxperiod1 + 1)
self.comb += self.period.eq(
Mux(self.selector, self.period1, self.period2))
self.comb += self.period1.eq(maxperiod1)
self.comb += self.period2.eq(maxperiod2)
self.sync += If(self.counter == 0, led.eq(~led),
self.counter.eq(self.period)).Else(
self.counter.eq(self.counter - 1))
self.led = led
def request(self, name, number=None):
resource = _lookup(self.available, name, number)
rt = _resource_type(resource)
if isinstance(rt, int):
obj = Signal(rt, name_override=resource[0])
else:
obj = Record(rt, name=resource[0])
for element in resource[2:]:
if isinstance(element, PlatformInfo):
obj.platform_info = element.info
break
self.available.remove(resource)
self.matched.append((resource, obj))
return obj
def request(self, name, number=None):
resource = _lookup(self.available, name, number)
rt = _resource_type(resource)
if isinstance(rt, int):
obj = Signal(rt, name_override=resource[0])
else:
obj = Record(rt, name=resource[0])
for element in resource[2:]:
if isinstance(element, PlatformInfo):
obj.platform_info = element.info
break
self.available.remove(resource)
self.matched.append((resource, obj))
return obj
class SafeInputMux(Module):
def __init__(self, inwidth):
wlog = int(log(inwidth, 2))
self.inputs = Array()
for i in range(inwidth):
self.inputs.append(Signal(1, name_override="input_{}".format(i)))
self.output = Signal(name_override="output")
self.selector = Signal(max=inwidth + 1)
self.io = set(self.inputs) | set([self.output, self.selector])
sel_r = Signal(max=inwidth + 1)
sel25 = Signal(max=1 << inwidth)
zero = Constant(0)
muxes = []
for i in range(len(self.inputs)):
x = Constant(1 << i, inwidth)
choose = Signal()
choose.eq(self.selector & x)
muxes.append(Mux(self.selector & x, self.inputs[i], zero))
mux = self.output.eq(reduce(orop, muxes))
self.comb += mux
self.sync += sel_r.eq(self.selector)
d = {}
x = 1
for i in range(inwidth):
d[i] = (sel25.eq(x << i), )
self.sync += If(
self.selector != sel_r,
sel25.eq(0),
).Else(Case(sel_r, d))
def gen_loopback_generic(self):
m = LoopbackTop(self.clk_freq, self.baud_rate)
# Mimic the platforms above and add a vendor-independent
# Clock Reset Generator
clk = Signal()
m.submodules += CRG(clk)
ios = {m.uart.tx, m.uart.rx, m.tx_led, m.rx_led, m.load_led,
m.take_led, m.empty_led, clk}
with open(self.output_file, "w") as fp:
fp.write(str(verilog.convert(m, ios=ios, name="uart")))
return [{'uart.v' : {'file_type' : 'verilogSource'}}]
def __init__(self, clk_freq, baud_rate):
self.submodules.uart = uart.Core(clk_freq, baud_rate)
self.rx_led = Signal()
self.tx_led = Signal()
self.load_led = Signal()
self.take_led = Signal()
self.empty_led = Signal()
self.comb += [self.tx_led.eq(~self.uart.tx),
self.rx_led.eq(~self.uart.rx),
self.load_led.eq(self.uart.sout.load),
self.take_led.eq(self.uart.sin.take),
self.empty_led.eq(self.uart.sin.empty)]
self.comb += [self.uart.out_data.eq(self.uart.in_data)]
self.sync += [
self.uart.wr.eq(0),
self.uart.rd.eq(0),
If(~self.uart.sin.empty,
self.uart.wr.eq(1),
self.uart.rd.eq(1)
)
]
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# Clk / Rst
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
def __init__(self,
platform,
sys_clk_freq,
with_sdram=False,
sdram_rate="1:2"):
self.sdram_rate = sdram_rate
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
if with_sdram:
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# Clk / Rst
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if with_sdram:
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(
self.cd_sys2x_ps, 2 * sys_clk_freq,
phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
if with_sdram:
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate ==
"1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"),
sdram_clk)
from d_flip_flop import Dflipflop
from migen.sim import run_simulation
from migen.fhdl.structure import Signal
ff_D = Signal()
ff_Q = Signal()
ff_Qi = Signal()
ff = Dflipflop(ff_D, ff_Q, ff_Qi)
def testbench():
yield ff_D.eq(1)
yield
yield ff_D.eq(0)
yield
yield
yield ff_D.eq(1)
yield
yield
yield
yield ff_D.eq(0)
yield
yield
run_simulation(ff, testbench(), vcd_name="test_d_ff.vcd")