def _inner_setup(self):
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError(
"Please download and save the vendor "
"SDRAM model in %s (not redistributable)" % i)
runner = icarus.Runner(extra_files=files)
#vcd = "test_%s.vcd" % self.__class__.__name__
vcd = None
self.sim = Simulator(self.tb, TopLevel(None), sim_runner=runner)
def _run(self, dummy_data, dummy_idle, max_burst_length, host_burst_length):
self.tb = TestBench("mt48lc16m16a2", dummy_data, dummy_idle, max_burst_length, host_burst_length)
# Verify that all necessary files are present
files = gather_files(self.tb)
for i in files:
if not os.path.exists(i):
raise FileNotFoundError("Please download and save the vendor "
"SDRAM model in %s (not redistributable)"
% i)
runner = icarus.Runner(extra_files=files)
vcd = "test_%s.vcd" % self.__class__.__name__
self.sim = Simulator(self.tb, TopLevel(vcd), sim_runner=runner)
with self.sim:
self.sim.run(10000)
# stop bit
selfp.pads.rx = 1
elif (i == 10):
selfp.pads.rx = 1
break
else:
selfp.pads.rx = 1 if (rx_value & 1) else 0
rx_value >>= 1
yield from self.wait_for(uart_period)
rx_value = ord(rx_string)
received_value = selfp.slave._r_rxtx.w
if (received_value == rx_value):
print("RX SUCCESS: ")
else:
print("RX FAILURE: ")
print("received " + chr(received_value))
while True:
yield
if __name__ == "__main__":
from migen.sim.generic import Simulator, TopLevel
from migen.sim import icarus
with Simulator(UARTTB(), TopLevel("top.vcd",
clk_period=int(1 / 0.08333333)),
icarus.Runner(keep_files=False)) as s:
s.run(20000)
self.byte_list = [(1,0x40), (0,0xCA), (1,0x10), (0, 0xFE), (1, 0x41)]
def do_simulation(self, s):
if s.cycle_counter > 5 and s.cycle_counter %2 and self.byte_list:
b = self.byte_list[0]
print("WR %s" % repr(b))
self.byte_list = self.byte_list[1:]
s.wr(self.tr.sink.stb, 1)
s.wr(self.tr.sink.payload.d, b[1])
s.wr(self.tr.sink.payload.rxcmd, b[0])
else:
s.wr(self.tr.sink.stb,0)
if s.rd(self.tr.source.stb):
print("%02x %d" % (s.rd(self.tr.source.payload.d), s.rd(self.tr.source.payload.rxcmd)))
if __name__ == "__main__":
from migen.sim.generic import Simulator, TopLevel
tl = TopLevel("sdram.vcd")
test = TestFilt(tl.clock_domains[0])
sim = Simulator(test, tl)
sim.run(500)
selfp.dut.rtlink.o.stb = 1 # falling edge at fine_ts = 0
yield
selfp.dut.rtlink.o.stb = 0
yield
self.check_output(selfp, data=0)
yield
self.check_output(selfp, data=0)
selfp.dut.rtlink.o.data = 1
selfp.dut.rtlink.o.fine_ts = 7
selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 7
yield
selfp.dut.rtlink.o.stb = 0
yield
self.check_output(selfp, data=0b10000000)
if __name__ == "__main__":
import sys
from migen.sim.generic import Simulator, TopLevel
if len(sys.argv) != 2:
print("Incorrect command line")
sys.exit(1)
cls = {"output": _OutputTB, "inout": _InOutTB}[sys.argv[1]]
with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1 / 0.125))) as s:
s.run()
t = self.tr.pop(0)
s.wr(self.ulpi_reg.raddr, t[1])
s.wr(self.ulpi_reg.rreq, 1)
if len(self.tw) > 0 and ~s.rd(self.ulpi_reg.wack) & ~s.rd(self.ulpi_reg.wreq) & s.cycle_counter >= self.tw[0][0]:
t = self.tw.pop(0)
s.wr(self.ulpi_reg.waddr, t[1])
s.wr(self.ulpi_reg.wreq, 1)
s.wr(self.ulpi_reg.wdata, t[2])
if s.rd(self.ulpi_reg.rack) & s.rd(self.ulpi_reg.rreq):
print("%06d TestULPI REGR [%02x] = %02x" % (s.cycle_counter, s.rd(self.ulpi_reg.raddr), s.rd(self.ulpi_reg.rdata)))
s.wr(self.ulpi_reg.rreq, 0)
if s.rd(self.ulpi_reg.wack) & s.rd(self.ulpi_reg.wreq):
print("%06d TestULPI REGW [%02x] = %02x" % (s.cycle_counter, s.rd(self.ulpi_reg.waddr), s.rd(self.ulpi_reg.wdata)))
s.wr(self.ulpi_reg.wreq, 0)
if s.rd(self.ulpi.data_out_source.stb):
print("%06d TestULPI [%02x] RXCMD=%d" % (s.cycle_counter, s.rd(self.ulpi.data_out_source.payload.d), s.rd(self.ulpi.data_out_source.payload.rxcmd)))
do_simulation.initialize = True
if __name__ == "__main__":
from migen.sim.generic import Simulator, TopLevel
tl = TopLevel("ulpi.vcd")
test = TestULPI(tl.clock_domains[0], True)
sim = Simulator(test, tl)
sim.run(5000)
#print(verilog.convert(test, set(ulpi_data.flatten()) | set(ulpi_reg.flatten()) ))
def setUp(self):
self.tb = TestBench()
vcd = None
#vcd = "test_producer.vcd"
self.sim = Simulator(self.tb, TopLevel(vcd, vcd_level=3))
def setUp(self):
self.tb = TestBench()
vcd = None
vcd = "test_cmdproc.vcd"
self.sim = Simulator(self.tb, TopLevel(vcd, vcd_level=3))
def main():
dut = Counter()
# Instantiating the generic top-level ourselves lets us
# specify a VCD output file.
sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
sim.run(20)
for i in packet(10, 0x20, 4):
yield i
for i in packet(10, 0x30, 2):
yield i
class SimSource(SimActor):
def __init__(self):
self.source = Endpoint(ULPI_DATA_D)
SimActor.__init__(self, gen())
self.submodules.w = Whacker(1024)
self.submodules.src = SimSource()
self.comb += self.src.source.connect(self.w.sink)
self.comb += self.src.busy.eq(0)
self.submodules.dmp = Dumper(D_LAST)
self.comb += self.w.source.connect(self.dmp.result)
self.comb += self.dmp.busy.eq(0)
if __name__ == '__main__':
from migen.sim.generic import Simulator, TopLevel
from migen.sim.icarus import Runner
tl = TopLevel("testwhacker.vcd")
tl.clock_domains[0].name_override = 'sys_clk'
test = TestWhacker()
sim = Simulator(test, tl, Runner(keep_files=True))
sim.run(2000)
def gen():
yield Token('source', {"start": 0, "count" : 4})
yield None
yield Token('source', {"start": 555, "count" : 77})
class SimSource(SimActor):
def __init__(self):
self.source = Source(dmatpl(1024))
SimActor.__init__(self, gen())
self.submodules.src = SimSource()
self.submodules.c = Consumer(self.port, 1024)
self.comb += self.c.sink.connect(self.src.source)
self.comb += self.src.busy.eq(0)
self.submodules.dmp = Dumper(D_LAST)
self.comb += self.c.source.connect(self.dmp.result)
self.comb += self.dmp.busy.eq(0)
if __name__ == '__main__':
from migen.sim.generic import Simulator, TopLevel
tl = TopLevel("testcons.vcd")
test = TestConsumer()
sim = Simulator(test, tl)
sim.run(200)
NET "{clk_ezusbfifo}" TNM_NET = "GRP_clk_ezusbfifo";
TIMESPEC "TS_cdc_fwd" =
FROM "GRP_clk_sys" TO "GRP_clk_ezusbfifo"
[delay] ns DATAPATHONLY;
TIMESPEC "TS_cdc_bwd" =
FROM "GRP_clk_ezusbfifo" TO "GRP_clk_sys"
[delay] ns DATAPATHONLY;
OFFSET = IN 15 ns VALID 30 ns BEFORE "{clk_if}";
OFFSET = OUT 15 ns AFTER "{clk_if}";
""".replace('[delay]',
str(0.5 * 33.33 * fraction[1] / fraction[0])),
clk_if=clk_if,
clk_sys=clk_sys,
clk_ezusbfifo=clk_ezusbfifo,
)
plat.build_cmdline(echo)
elif command == 'sim':
from migen.sim.generic import Simulator, TopLevel
echo = Echo(SimUSBActor(loop=True))
sim = Simulator(echo, TopLevel("echo.vcd"))
with sim:
sim.run()
else:
print('usage: python %s build|sim [options]' % sys.argv[0])
