def main():
# Create graph
g = DataFlowGraph()
gen1 = ComposableSource(g, NumberGen())
gen2 = ComposableSource(g, NumberGen())
ps = gen1 + gen2
result = ps*gen1 + ps*gen2
g.add_connection(result.actor_node, ActorNode(Dumper()))
gen1.actor_node.actor.name = "gen1"
gen2.actor_node.actor.name = "gen2"
result.actor_node.name = "result"
# Elaborate
print("is_abstract before elaboration: " + str(g.is_abstract()))
draw(g)
g.elaborate()
print("is_abstract after elaboration : " + str(g.is_abstract()))
draw(g)
# Simulate
c = CompositeActor(g)
fragment = c.get_fragment()
sim = Simulator(fragment, Runner())
sim.run(100)
def main(): nbits = 32 # See: # http://www.csse.monash.edu.au/~damian/Idioms/Topics/12.1.DataFlow/html/text.html g = DataFlowGraph() adder = ActorNode(Add(BV(nbits))) bufadd = ActorNode(plumbing.Buffer) # TODO FIXME: deadlocks without this buffer init1 = ActorNode(Init(nbits)) buf1 = ActorNode(plumbing.Buffer) init2 = ActorNode(Init(nbits)) buf2 = ActorNode(plumbing.Buffer) g.add_connection(adder, bufadd) g.add_connection(bufadd, init1) g.add_connection(init1, buf1) g.add_connection(buf1, adder, sink_subr="a") g.add_connection(buf1, init2) g.add_connection(init2, buf2) g.add_connection(buf2, adder, sink_subr="b") g.add_connection(bufadd, ActorNode(Dumper(nbits))) c = CompositeActor(g) fragment = c.get_fragment() sim = Simulator(fragment, Runner()) sim.run(100)
def main():
dut = Counter()
# Use the Icarus Verilog runner.
# We do not specify a top-level object, and use the default.
sim = Simulator(dut.get_fragment(), Runner())
# Since we do not use sim.interrupt, limit the simulation
# to some number of cycles.
sim.run(20)
def main():
# The "wishbone.Initiator" library component runs our generator
# and manipulates the bus signals accordingly.
master = wishbone.Initiator(my_generator())
# Our slave.
slave = MyPeripheral()
# The "wishbone.Tap" library component examines the bus at the slave port
# and displays the transactions on the console (<TRead...>/<TWrite...>).
tap = wishbone.Tap(slave.bus)
# Connect the master to the slave.
intercon = wishbone.InterconnectPointToPoint(master.bus, slave.bus)
# A small extra simulation function to terminate the process when
# the initiator is done (i.e. our generator is exhausted).
def end_simulation(s):
s.interrupt = master.done
fragment = autofragment.from_local() + Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def test_writer():
print("*** Testing writer")
trgen = SimActor(trgen_gen(), ("address_data", Source, [("a", BV(30)), ("d", BV(32))]))
writer = dma_wishbone.Writer()
g = DataFlowGraph()
g.add_connection(trgen, writer)
comp = CompositeActor(g)
peripheral = MyPeripheral()
tap = wishbone.Tap(peripheral.bus)
interconnect = wishbone.InterconnectPointToPoint(writer.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = trgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ tap.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()
def test_reader():
print("*** Testing reader")
adrgen = SimActor(adrgen_gen(), ("address", Source, [("a", BV(30))]))
reader = dma_wishbone.Reader()
dumper = SimActor(dumper_gen(), ("data", Sink, [("d", BV(32))]))
g = DataFlowGraph()
g.add_connection(adrgen, reader)
g.add_connection(reader, dumper)
comp = CompositeActor(g)
peripheral = MyPeripheral()
interconnect = wishbone.InterconnectPointToPoint(reader.bus, peripheral.bus)
def end_simulation(s):
s.interrupt = adrgen.done and not s.rd(comp.busy)
fragment = comp.get_fragment() \
+ peripheral.get_fragment() \
+ interconnect.get_fragment() \
+ Fragment(sim=[end_simulation])
sim = Simulator(fragment, Runner())
sim.run()