def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
self.platform.request("eth"),
clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
(ethmac_nrxslots + ethmac_ntxslots) * 0x800)
self.crg.cd_sys.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
# period constraints are required here because of vivado
self.platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk,
eth_clocks.rx)
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
eth = self.platform.request("eth_mii")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
eth, clk_freq=self.clk_freq)
self.comb += eth.mdc.eq(0)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone",
nrxslots=ethmac_nrxslots, ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF_inst/O]")
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_rx_IBUF_inst/O]")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 40.0)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 40.0)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk, self.ethphy.crg.cd_eth_rx.clk)
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
platform = self.platform
if platform.name == "mixxeo":
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
self.csr_devices.append("leds")
if platform.name == "m1":
self.submodules.buttons = gpio.GPIOIn(
Cat(platform.request("user_btn", 0),
platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", i) for i in range(2)))
self.csr_devices += ["buttons", "leds"]
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone")
self.add_wb_slave(self.mem_map["ethmac"], 0x2000, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
with_preamble_crc=False)
self.add_wb_slave(self.mem_map["ethmac"], 0x2000, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
def __init__(self, *args, ethmac_nrxslots=2, ethmac_ntxslots=2, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")
eth_clocks = self.platform.request("eth_clocks")
self.submodules.ethphy = LiteEthPHY(eth_clocks,
self.platform.request("eth"),
clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy,
dw=32,
interface="wishbone",
nrxslots=ethmac_nrxslots,
ntxslots=ethmac_ntxslots)
ethmac_len = (ethmac_nrxslots + ethmac_ntxslots) * 0x800
self.add_wb_slave(self.mem_map["ethmac"], ethmac_len, self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"] | self.shadow_base,
ethmac_len)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_tx.clk,
eth_clocks.rx)